Intel Agilex User Manual page 68

Variable precision dsp blocks
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4.2.1.1. FP32 Operation Modes Supported Register Configurations
Table 26.
Supported Register Configurations For FP32 Multiplication Mode
Latency
fp32_mult_a_clk
0
Disable
1
Enable
1
Disable
2
Enable
≥3
Disable
Table 27.
Supported Register Configurations For FP32 Addition or Subtraction Mode
Latency
Data Input Register
fp32_adder_a
_clken
0
Disable
1
Enable
1
Disable
2
Enable
≥3
Enable
Table 28.
Supported Register Configurations For FP32 Multiplication with Addition or
Subtraction Mode
Latency
Data Input Register
fp32_add
er_a_clke
n
0
Disable
1
Enable
1
Disable
2
Enable
≥3
Enable
≥4
Enable
®
Intel
Agilex
Variable Precision DSP Blocks User Guide
68
4. Intel Agilex Variable Precision DSP Blocks Design Considerations
Input Register
fp32_mult_b_clk
en
en
Disable
Enable
Disable
Enable
Enable
fp32_adder_b
fp32_adder_a
_clken
_chainin_pl_cl
Disable
Enable
Disable
Enable
Enable
Adder 1st
Pipeline
Register
fp32_mul
fp32_mul
fp32_add
t_a_clken
t_b_clken
er_a_chai
nin_pl_cl
ken
Disable
Disable
Disable
Enable
Enable
Disable
Disable
Disable
Disable
Enable
Enable
Disable
Enable
Enable
Disable,
enable
Enable
Enable
Disable,
enable
Pipeline Register
mult_pipeline_cl
mult_2nd_pipelin
ken
Disable
Disable
Disable
Disable
Disable, enable
Pipeline Register
fp32_adder_a
_chainin_2nd_
ken
pl_clken
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable, enable
Disable, enable
Adder
Multiplier
2nd
1st
Pipeline
Pipeline
Register
Register
fp32_add
mult_pipe
er_a_chai
line_clke
nin_2nd_
n
pl_clken
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable,
Disable
enable
Disable,
Disable,
enable
enable
UG-20213 | 2019.04.02
Output Register
output_clken
e_clken
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Adder Input
Output
Register
Register
adder_input_c
output_clken
lken
Disable
Disable
Disable
Disable
Disable
Enable
Disable
Enable
Enable
Enable
Multiplier
Adder
2nd
Input
Pipeline
Register
Register
mult_2nd
adder_inp
output_cl
_pipeline
ut_clken
_clken
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Disable
Disable
Enable
Disable
Enable
Enable
Enable
Enable
Enable
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Output
Register
ken

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