Figure 10. I 2 C Point-To-Point Topology; Table 7. I 2 C Point-To-Point Platform Routing Guidelines - Intel Quark SE Series Platform Manual

Figure 10. I 2 C Point-to-Point Topology
The following table shows detailed routing requirements for the I
Table 7. I 2 C Point-to-Point Platform Routing Guidelines
Leveraged from Intel® Quark™ SoC
Transmission Line Segment
Routing Layer (Microstrip/Stripline)
Characteristic Impedance
Trace Width (w)
Trace Spacing (S1): Between SPI signals
Trace Spacing (S2): Between SPI signals
and other signals
Trace Length
Total Trace Length
Reference
Pull-up Resistor Rpu
Intel® Quark™ SE Microcontroller C1000
Platform Design Guide
26
I 2 C (SDA, SCL)
I 2 C
Breakout
Breakoutsoc
MS/SL
50Ω + 10% (MS)
50Ω + 10% (SL)
Meet impedance or
3.5 mils minimum
4 mils
5 mils
<500 mils
<15000 mils; Ctotal <400pF
VSS referencing
Refer to table below
Document Number: 334715-004EN
I2C Interface
2 C bus.
Segment trace
L1-L4
MS/SL
50Ω + 10% (MS)
50Ω + 10% (SL)
Meet impedance
2W
2W
15000 mils
June 2017