Intel Agilex User Manual page 58

Figure 41. Direct Vector Dot Product Using FP16 Half-Precision Floating-Point Arithmetic
3.2.3.3. Complex Multiplication
The Intel Agilex devices support the floating-point arithmetic single precision complex
multiplier using four Intel Agilex variable-precision DSP blocks.
Figure 42. Sample of Complex Multiplication Equation
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
58
3. Intel Agilex Variable Precision DSP Blocks Operational Modes
Connect this signal to
fp32_chainin[31:0]
the fp32_chainout signal
of the next DSP in the chain
Connect this signal to
Input
the fp32_result signal fp32_adder_a[31:0]
Register
of the next DSP in the chain
Bank
Vector One
fp16_mult_top_a[15:0]
U fp32_chainout[31:0]
V fp16_mult_top_b[15:0]
Top
*Pipeline
*Pipeline *Pipeline
Multiplier
Register
Register
Register
W fp16_mult_bot_a[15:0]
X fp16_mult_bot_b[15:0]
Bottom
Multiplier
Vector Two
fp32_chainout[31:0]
fp32_chainin[31:0]
Input
fp32_adder_a[31:0]
QR+ST+UV+WX+YZ+ab+cd+ef QR+ST+UV+WX+YZ+ab+cd+ef
Register
Bank
fp16_mult_top_a[15:0]
Q I
fp16_mult_top_b[15:0]
R
Top
*Pipeline
*Pipeline
*Pipeline
Multiplier
Register
Register
Register
S
fp16_mult_bot_a[15:0]
fp16_mult_bot_b[15:0]
T
Bottom
Multiplier
Vector One
fp32_chainout[31:0]
fp32_chainin[31:0]
Input
AB + CD+EF+GH+IJ+KL+MN+OP fp32_adder_a[31:0]
Register
Bank
Vector One
fp16_mult_top_a[15:0]
M fp32_chainout[31:0]
N fp16_mult_top_b[15:0]
Top
*Pipeline *Pipeline
*Pipeline
Multiplier
Register
Register
Register
O fp16_mult_bot_a[15:0]
P fp16_mult_bot_b[15:0]
Bottom
Multiplier
Vector Two
fp32_chainout[31:0]
fp32_chainin[31:0]
Input
IJ+KL+MN+OP fp32_adder_a[31:0]
Register
Bank
I I fp16_mult_top_a[15:0]
fp16_mult_top_b[15:0]
J
Top
*Pipeline
*Pipeline *Pipeline
Multiplier
Register Register
Register
K fp16_mult_bot_a[15:0]
fp16_mult_bot_b[15:0]
L
Bottom
Multiplier
Vector One
fp32_chainout[31:0]
fp32_chainin[31:0]
Input
AB + CD+EF+GH
fp32_adder_a[31:0]
Register
Bank
Vector One
E fp16_mult_top_a[15:0] fp32_chainout[31:0]
fp16_mult_top_b[15:0]
F
Top
*Pipeline
*Pipeline *Pipeline
Multiplier
Register
Register
Register
G fp16_mult_bot_a[15:0]
fp16_mult_bot_b[15:0]
H
Bottom
Multiplier
Vector Two
fp32_chainout[31:0]
fp32_chainin[31:0]
Input
fp32_adder_a[31:0]
Register
Bank
A fp16_mult_top_a[15:0]
fp16_mult_top_b[15:0]
B
Top
*Pipeline
*Pipeline *Pipeline
Multiplier
Register
Register
Register
C fp16_mult_bot_a[15:0]
D fp16_mult_bot_b[15:0]
Bottom
Multiplier
Sum of Two FP16 Multiplication with
FP32 Addition
*This block diagram shows the functional representation of the DSP block.
The pipeline registers are embedded within the various circuits of the DSP block.
*Pipeline *Pipeline *Pipeline
Register Register
Register
Adder
Output
fp32_result[31:0]
Register fp16_mult_top_invalid
Bank fp16_mult_top_inexact
fp16_mult_top_overflow
fp16_mult_top_underflow
Adder fp16_mult_top_infinite(extended format)
fp16_mult_top_zero(extended format)
Register
fp16_mult_bot_invalid
fp16_mult_bot_inexact
fp16_mult_bot_overflow
fp16_mult_bot_underflow
fp16_mult_bot_infinite(extended format)
fp16_mult_bot_zero(extended format)
*Pipeline *Pipeline
*Pipeline
Register Register
Register
Adder
Output
fp32_result[31:0] QR+ST+UV+WX
Register fp16_mult_top_invalid
fp16_mult_top_inexact
Bank
fp16_mult_top_overflow
fp16_mult_top_underflow
Adder fp16_mult_top_infinite(extended format)
fp16_mult_top_zero(extended format)
Register
fp16_mult_bot_invalid
fp16_mult_bot_inexact
fp16_mult_bot_overflow
fp16_mult_bot_underflow
fp16_mult_bot_infinite(extended format)
fp16_mult_bot_zero(extended format)
*Pipeline *Pipeline *Pipeline
Register Register
Register
Adder
Output AB + CD + EF + GH + IJ + KL + MN + OP+QR+ST+UV+WX+YZ+ab+cd+ef
fp32_result[31:0]
fp16_mult_top_invalid
Register
fp16_mult_top_inexact
Bank
fp16_mult_top_overflow
fp16_mult_top_underflow
Adder fp16_mult_top_infinite(extended format)
fp16_mult_top_zero(extended format)
Register
fp16_mult_bot_invalid
fp16_mult_bot_inexact
fp16_mult_bot_overflow
fp16_mult_bot_underflow
fp16_mult_bot_infinite(extended format)
fp16_mult_bot_zero(extended format)
*Pipeline *Pipeline *Pipeline
Register Register
Register
Adder
Output fp32_result[31:0]
IJ+KL+MN+OP
fp16_mult_top_invalid
Register
Bank fp16_mult_top_inexact
fp16_mult_top_overflow
fp16_mult_top_underflow
fp16_mult_top_infinite(extended format)
Adder
fp16_mult_top_zero(extended format)
Register
fp16_mult_bot_invalid
fp16_mult_bot_inexact
fp16_mult_bot_overflow
fp16_mult_bot_underflow
fp16_mult_bot_infinite(extended format)
fp16_mult_bot_zero(extended format)
*Pipeline *Pipeline
*Pipeline
Register Register
Register
Adder
AB + CD + EF + GH + IJ + KL + MN + OP
Output fp32_result[31:0]
Register fp16_mult_top_invalid
fp16_mult_top_inexact
Bank
fp16_mult_top_overflow
fp16_mult_top_underflow
fp16_mult_top_infinite(extended format)
Adder
Register fp16_mult_top_zero(extended format)
fp16_mult_bot_invalid
fp16_mult_bot_inexact
fp16_mult_bot_overflow
fp16_mult_bot_underflow
fp16_mult_bot_infinite(extended format)
fp16_mult_bot_zero(extended format)
*Pipeline *Pipeline *Pipeline
Register Register
Register
Adder
fp32_result[31:0] (A*B) + (C*D)+(E*F)+(H*G)
Output
Register fp16_mult_top_invalid
Bank fp16_mult_top_inexact
fp16_mult_top_overflow
fp16_mult_top_underflow
Adder fp16_mult_top_infinite(extended format)
Register fp16_mult_top_zero(extended format)
fp16_mult_bot_invalid
fp16_mult_bot_inexact
fp16_mult_bot_overflow
fp16_mult_bot_underflow
fp16_mult_bot_infinite(extended format)
fp16_mult_bot_zero(extended format)
fp32_chainout[31:0]
UG-20213 | 2019.04.02
fp16_adder_invalid
fp16_adder_inexact
fp16_adder_overflow
fp16_adder_underflow
fp16_adder_infinite(extended format)
fp16_adder_zero(extended format)
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
fp16_adder_invalid
fp16_adder_inexact
fp16_adder_overflow
fp16_adder_underflow
fp16_adder_infinite(extended format)
fp16_adder_zero(extended format)
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
fp16_adder_invalid
fp16_adder_inexact
fp16_adder_overflow
fp16_adder_underflow
fp16_adder_infinite(extended format)
fp16_adder_zero(extended format)
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
fp16_adder_invalid
fp16_adder_inexact
fp16_adder_overflow
fp16_adder_underflow
fp16_adder_infinite(extended format)
fp16_adder_zero(extended format)
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
fp16_adder_invalid
fp16_adder_inexact
fp16_adder_overflow
fp16_adder_underflow
fp16_adder_infinite(extended format)
fp16_adder_zero(extended format)
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
fp16_adder_invalid
fp16_adder_inexact
fp16_adder_overflow
fp16_adder_underflow
fp16_adder_infinite(extended format)
fp16_adder_zero(extended format)
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
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