Intel Agilex User Manual page 10

Figure 1. Fixed-Point Arithmetic 9 x 9 Mode
DISABLE_CHAINOUT
LOADCONST
ACCUMULATE
ay[8..0]
ax[8..0]
by[8..0]
bx[8..0]
cy[8..0]
cx[8..0]
dy[8..0]
dx[8..0]
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
10
2. Intel Agilex Variable Precision DSP Blocks Architecture
1st Multiplier
x
1st Adder
+
x
2nd Multiplier
3rd Multiplier
x
2nd Adder
+
x
4th Multiplier
*This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.
CLK
chainin[63..0]
ENA[2..0]
CLR[1..0]
+
+
Chainout adder
Adder
64'b0
1 0
chainout[63..0]
UG-20213 | 2019.04.02
Constant
Double
Accumulation
Register
resulta[36:0]
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