Intel Agilex User Manual page 65

4. Intel Agilex Variable Precision DSP Blocks Design Considerations
UG-20213 | 2019.04.02
input register must be enabled when top delay register is enabled. The clock enable
for both registers must be the same. Similarly, the
when bottom delay register is enabled. The clock enable for both registers must be
the same.
The delay registers are only supported in 18 x 18 or 18 x 19 independent multiplier,
multiplier adder sum mode and 18-bit systolic FIR mode.
Figure 47. Input Cascade in Fixed-Point Arithmetic 18 x 19 Mode
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scanin[18..0]
ay[18..0]
az[17..0]
ax[17..0]
Top delay registers
by[18..0]
bz[17..0]
bx[17..0]
Bottom delay registers
Intel
input register must be enabled
by
CLK
ENA[2..0]
CLR[0]
scanout[18..0]
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Agilex Variable Precision DSP Blocks User Guide
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