Interface Routing Guidelines; Figure 12. I²C Point-To-Point Topology; Table 5. I²C Point-To-Point Platform Routing Guidelines - Intel Quark D2000 Design Manual

I²C Interface
 Hardware Handshake Interface to support DMA capability
 Interrupt Control
 FIFO support with 16B deep RX and TX FIFOs
4.2

Interface Routing Guidelines

I²C clock and data signals require pull-up resistors. The pull-up size is dependent on
the bus capacitive load (this includes all device leakage currents).
Figure 12. I²C Point-to-Point Topology
The following table shows detailed routing requirements for the I²C bus.
Table 5. I²C Point-to-Point Platform Routing Guidelines
Leveraged from Intel®
I²C (SDA, SCL)
Transmission Line
Segment
Routing Layer
(Microstrip/Stripline)
Characteristic Impedance
Trace Width (w)
Trace Spacing (S):
Between SPI signals
Trace Spacing (S2):
Between SPI signals and
other signals
Trace Length
Pull-up Resistor Rpu
NOTES:
1.
2.
3.
November 2016
Document Number: 333580-002EN
Quark™ SoC
50Ω + 10% (MS)
50Ω + 10% (SL)
Meet impedance
5 mil minimum
5 mil minimum
Length matching between Data and Clk is 540 mils
Load = routing length capacitance + MCP = device pin capacitance
MCP + device pin capacitance = 10 µF
I²C
BRK OUT Main
L1 L2
MS/SL MS/SL
50Ω + 10% (MS)
50Ω + 10% (SL)
Meet impedance
2*w
3*w
0.5" max See below
See below
Intel® Quark™ Microcontroller D2000
BRK IN
L3
MS/SL
50Ω + 10% (MS)
50Ω + 10% (SL)
Meet impedance
5 mil minimum
5 mil minimum
0.5" max
Platform Design Guide
21