Intel Agilex User Manual page 46

•
fp16_mult_bot_invalid
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fp16_mult_bot_inexact
•
fp16_mult_bot_overflow
•
fp16_mult_bot_underflow
•
fp16_adder_invalid
•
fp16_adder_inexact
•
fp16_adder_overflow
•
fp16_adder_underflow
The following are exception flags supported in extended format:
•
fp16_mult_top_invalid
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fp16_mult_top_inexact
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fp16_mult_top_infinite
•
fp16_mult_top_zero
•
fp16_mult_bot_invalid
•
fp16_mult_bot_inexact
•
fp16_mult_bot_infinite
•
fp16_mult_bot_zero
•
fp16_adder_invalid
•
fp16_adder_inexact
•
fp16_adder_infinite
•
fp16_adder_zero
Figure 33. Sum of Two FP16 Multiplication Mode
fp16_mult_top_a[15:0]
fp16_mult_top_b[15:0]
fp16_mult_bot_a[15:0]
fp16_mult_bot_b[15:0]
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
46
3. Intel Agilex Variable Precision DSP Blocks Operational Modes
Input
Register
Top
Bank *Pipeline
*Pipeline
Multiplier
Register
Register
Bottom
Multiplier
*This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.
Adder
*Pipeline Register
Register
fp32_chainout[31:0]
UG-20213 | 2019.04.02
fp32_result[31:0]
Output
fp16_mult_top_invalid
Register fp16_mult_top_inexact
Bank
fp16_mult_top_overflow
fp16_mult_top_underflow
fp16_mult_top_infinite(extended mode)
fp16_mult_top_zero(extended mode)
fp16_mult_bot_invalid
fp16_mult_bot_inexact
fp16_mult_bot_overflow
fp16_mult_bot_underflow
fp16_mult_bot_infinite(extended mode)
fp16_mult_bot_zero(extended mode)
fp16_adder_invalid
fp16_adder_inexact
fp16_adder_overflow
fp16_adder_underflow
fp16_adder_infinite(extended mode)
fp16_adder_zero(extended mode)
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