Intel Agilex User Manual page 36

Figure 21. One 18 × 19 Complex Multiplier with Two Variable Precision DSP Blocks for
Intel Agilex Devices
c[18..0]
b[17..0]
d[18..0]
a[17..0]
d[18..0]
b[17..0]
c[18..0]
a[17..0]
3.1.4.1. 18 × 19 Multiplication Summed with 36-Bit Input Mode
Intel Agilex variable precision DSP blocks support one 18 × 19 multiplication summed
to a 36-bit input.
The 18 × 19 multiplication summed with 36-bit input mode uses the equations:
• resulta = (ax * ay) + bx to sum the 18 x 19 multiplication with 36-bit input.
• resulta = (ax * ay) - bx to subtract the 18 x 19 multiplication with 36-bit input.
Use the upper multiplier to provide the input for an 18 × 19 multiplication, while the
bottom multiplier is bypassed. The
Use the
SUB
subtraction operation.
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
36
3. Intel Agilex Variable Precision DSP Blocks Operational Modes
Variable-Precision DSP Block 1
19
18
19
18
Variable-Precision DSP Block 2
19
18
19
18
*This block diagram shows the functional representation of the DSP block.
The pipeline registers are embedded within the various circuits of the DSP block.
bx[35..0]
dynamic control signal to control the adder to perform addition or
Multiplier
x
Adder
+
Multiplier
x
Multiplier
x
Adder
-
Multiplier
x
signals the 36-bit input operand.
UG-20213 | 2019.04.02
38
Imaginary Part
(ad+bc)
38
Real Part
(ac-bd)
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