Intel Agilex User Manual page 39

3. Intel Agilex Variable Precision DSP Blocks Operational Modes
UG-20213 | 2019.04.02
Figure 26. 18-Bit Systolic FIR Mode for Intel Agilex Devices
ay[18..0]
az[17..0]
ax[17..0]
COEFSELA[2..0]
by[18..0]
bz[17..0]
bx[17..0]
COEFSELB[2..0]
3.1.5.3. 27-Bit Systolic FIR Mode
In 27-bit systolic FIR mode, the chainout adder or accumulator is configured for a
64-bit operation, providing 10 bits of overhead when using a 27-bit data (54-bit
products). This allows a total of eleven 27 x 27 multipliers or eleven Intel Agilex
variable precision DSP blocks to be cascaded as systolic FIR structure.
The 27-bit systolic FIR mode allows the implementation of one stage systolic filter per
DSP block. Systolic registers are not required in this mode.
Figure 27. 27-Bit Systolic FIR Mode for Intel Agilex Devices
COEFSELA[2..0]
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Pre-Adder
19
+/-
18
18
3
Internal
Coefficient
Pre-Adder
19
+/-
18
18
3
Internal
Coefficient
*This block diagram shows the functional representation of the DSP block.
The pipeline registers are embedded within the various circuits of the DSP block.
Pre-Adder
26
ay[25..0]
+/-
26
az[25..0]
27
ax[26..0]
3
*This block diagram shows the functional representation of the DSP block.
The pipeline registers are embedded within the various circuits of the DSP block.
chainin[43..0]
44
Systolic Systolic
Multiplier
Registers Register
x
+/- +/-
Systolic
Adder Chainout adder or
Registers
accumulator
Multiplier
x
18-bit Systolic FIR
chainin[63..0]
64
Multiplier
27
x
+
Internal
Chainout adder or
Coefficient
accumulator
27-bit Systolic FIR
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
+
44
resulta[43..0]
44
chainout[43..0]
64
resulta[63..0]
64
chainout[63..0]
39