Intel Agilex User Manual page 38

In systolic FIR mode, the input of the multiplier can come from four different sets of
sources:
• Two dynamic inputs
• One dynamic input and one coefficient input
• One coefficient input and one pre-adder output
• One dynamic input and one pre-adder output
3.1.5.1. Mapping Systolic Mode User View to Variable Precision Block
Architecture View
The following figure shows implementation of the systolic FIR filter (a) using the Intel
Agilex variable precision DSP blocks (d) by retiming the register and restructuring the
adder. Register B can be retimed into systolic registers at the chainin, ay and ax input
paths as shown in (b). The end result of the register retiming is shown in (c). The
location of the adder is then restructured to sum both the multipliers output. The
adder result is send to chainout adder to sum with the chainin value from the previous
DSP block as shown in (d).
Figure 25. Mapping Systolic Mode User View to Variable Precision Block Architecture
View
(a) Systolic FIR Filter
User View
x[n]
c1
x[n-2]
c2
x[n-4]
c3
x[n-6]
c4
3.1.5.2. 18-bit Systolic FIR Mode
In 18-bit systolic FIR mode, the adders are configured as dual 44-bit adders, thereby
giving 7 bits of overhead when using an 18 x 19 operation mode, resulting 37-bit
result. This allows a total sixteen 18 x 19 multipliers or eight Intel Agilex variable
precision DSP blocks to be cascaded as systolic FIR structure.
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
38
3. Intel Agilex Variable Precision DSP Blocks Operational Modes
(b) Variable Precision Block
Architecture View (Before Retiming)
dataa_y0 x[n] w1[n]
w1[n]
dataa_x0 c1
Multiplier
datab_y1 x[n-2] w2[n]
w2[n]
datab_x1 c2
Multiplier
Output
Register A
Register A
Register
Bank
w3[n]
First DSP Block Result
Chainin from
Register B
Previous DSP Block
w4[n] w3[n]
dataa_y0 x[n-4]
Chainout
Adder
dataa_x0 c3
Register A
Register B
y[n]
datab_y1 x[n-6]
w4[n]
datab_x1 c4
Output
Register
Register C
Bank
Result
y[n]
Second DSP Block
(c) Variable Precision Block
Architecture View (After Retiming)
dataa_y0 x[n] w1[n]
dataa_x0 c1
Multiplier
datab_y1 x[n-2] w2[n]
Adder Adder
datab_x1 c2
Multiplier
Output
Register A
Register
Bank
First DSP Block Result
Chainin from
Previous DSP Block
Systolic
Systolic
Registers Register B
Register
dataa_y0 x[n-4]
w3[n]
Chainout
Adder
Retiming
dataa_x0 c3
datab_y1 x[n-6] w4[n]
datab_x1 c4
Output
Register
Register C
Bank
Result
y[n]
Second DSP Block
UG-20213 | 2019.04.02
(d) Variable Precision Block
Architecture View (Adder Restructured)
dataa_y0 x[n] w1[n]
dataa_x0 c1
Multiplier
datab_y1 x[n-2] w2[n]
Adder
datab_x1 c2
Multiplier
Output
Register
Register A
Bank
First DSP Block Result
Chainin from
Previous DSP Block
Systolic
Systolic
Registers Register B
Register
dataa_y0 x[n-4]
w3[n]
dataa_x0 c3
Chainout
Adder
Adder
datab_y1 x[n-6] w4[n]
datab_x1 c4
Output
Register
Register C
Bank
Result
y[n]
Second DSP Block
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