Intel Agilex User Manual page 42

Figure 30. Multiply Accumulate Mode for Intel Agilex Devices
fp32_chainin[31:0]
accumulate
fp32_adder_a[31:0]
fp32_adder_b[31:0]
fp32_mult_a[31:0]
fp32_mult_b[31:0]
3.2.1.4. FP32 Vector One Mode
This mode performs floating-point multiplication followed by floating-point addition or
subtraction with the chainin input from the previous variable DSP Block. Input
fp32_adder_a
Table 16. Equations Applied to FP32 Vector One Mode
Chainin Parameter
Disable
Enable
The FP32 vector one mode supports the following exception flags:
•
fp32_mult_invalid
•
fp32_mult_inexact
•
fp32_mult_overflow
•
fp32_mult_underflow
•
fp32_adder_invalid
•
fp32_adder_inexact
•
fp32_adder_overflow
•
fp32_adder_underflow
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
42
3. Intel Agilex Variable Precision DSP Blocks Operational Modes
*Pipeline
Input
Register
Bank
*Pipeline *Pipeline
Register Register
Bank Bank
Multiplier
*This block diagram shows the functional representation of the DSP block.
The pipeline registers are embedded within the various circuits of the DSP block.
is directly fed into chainout.
Vector One with Floating-Point
Addition
result =
fp32_mult_a
fp32_mult_b
Chainout =
fp32_adder_a
result = (
fp32_mult_a
) +
fp32_mult_b fp32_chainin
Chainout =
fp32_adder_a
*Pipeline
Register Register
*Pipeline
Bank Bank
Adder
Register
Bank
fp32_chainout[31:0]
Vector One with Floating-Point
* result =
fp32_mult_b
Chainout =
* result = (
fp32_mult_b
Chainout =
UG-20213 | 2019.04.02
Output
fp32_result[31:0]
Register
fp32_mult_invalid
Bank
fp32_mult_inexact
fp32_mult_overflow
fp32_mult_underflow
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
Subtraction
*
fp32_mult_a
fp32_adder_a
*
fp32_mult_a
) -
fp32_chainin
fp32_adder_a
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