Intel Agilex User Manual page 69

4. Intel Agilex Variable Precision DSP Blocks Design Considerations
UG-20213 | 2019.04.02
Table 29. Supported Register Configurations For FP32 Multiplication with Accumulation
Mode
Latency Data Input Register
accumul fp32_mu
ate_clke lt_a_clk
n
1 Disable Disable
2 Enable Enable
≥3 Enable Enable
≥4 Enable Enable
Table 30. Supported Register Configurations For FP32 Vector One Mode
Latency Data Input Register
fp32_add
er_a_clke
n
0 Disable
1 Enable
1 Disable
2 Enable
≥3 Enable
≥4 Enable
Table 31. Supported Register Configurations For FP32 Vector Two Mode
Latency Data Input Register
fp32_add
er_a_clke
n
0 Disable
1 Enable
1 Disable
2 Enable
≥3 Enable
Send Feedback
Adder
1st
Pipeline
Register
fp32_mu accum_p
lt_b_clk ipeline_c
en en lken
Disable Disable
Enable Disable
Enable Disable,
enable
Enable Disable,
enable
Adder 1st
Pipeline
Register
fp32_mul fp32_mul fp32_add
t_a_clken t_b_clken er_a_chai
nin_pl_cl
ken
Disable Disable Disable
Enable Enable Disable
Disable Disable Disable
Enable Enable Disable
Enable Enable Disable,
enable
Enable Enable Disable,
enable
Adder 1st
Pipeline
Register
fp32_mul fp32_mul fp32_add
t_a_clken t_b_clken er_a_chai
nin_pl_cl
ken
Disable Disable Disable
Enable Enable Disable
Disable Disable Disable
Enable Enable Disable
Enable Enable Disable,
enable
Adder Multiplie Multiplie
2nd r 1st r 2nd
Pipeline Pipeline Pipeline
Register Register Register
accum_2 mult_pip mult_2n
nd_pipel eline_clk d_pipeli
ine_clke en ne_clken
n
Disable Disable Disable
Disable Disable Disable
Disable, Disable Disable
enable
Disable, Disable, Enable
enable enable
Adder Multiplier
2nd 1st
Pipeline Pipeline
Register Register
fp32_add mult_pipe
er_a_chai line_clke
nin_pl_cl n
ken
Disable Disable
Disable Disable
Disable Disable
Disable Disable
Disable, Disable
enable
Disable, Disable,
enable enable
Adder Multiplier
2nd 1st
Pipeline Pipeline
Register Register
fp32_add mult_pipe
er_a_chai line_clke
nin_pl_cl n
ken
Disable Disable
Disable Disable
Disable Disable
Disable Disable
Disable, Disable,
enable enable
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
Adder Input Output
Register Register
accum_a adder_in output_c
dder_clk put_clke lken
en n
Disable Disable Enable
Disable Disable Enable
Enable Enable Enable
Enable Enable Enable
Multiplier Adder Output
2nd Input Register
Pipeline Register
Register
mult_2nd adder_inp output_cl
_pipeline ut_clken ken
_clken
Disable Disable Disable
Disable Disable Disable
Disable Disable Enable
Disable Disable Enable
Disable Enable Enable
Enable Enable Enable
Multiplier Adder Output
2nd Input Register
Pipeline Register
Register
mult_2nd adder_inp output_cl
_pipeline ut_clken ken
_clken
Disable Disable Disable
Disable Disable Disable
Disable Disable Enable
Disable Disable Enable
Enable Enable Enable
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