Intel Agilex User Manual page 61

3. Intel Agilex Variable Precision DSP Blocks Operational Modes
UG-20213 | 2019.04.02
Figure 46. Complex Multiplication with Result Real Using FP16 Half-Precision Floating-
Point Arithmetic
b fp16_mult_top_a[15:0]
fp16_mult_top_b[15:0]
d
a fp16_mult_bot_a[15:0]
c fp16_mult_bot_b[15:0]
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Input
Register
Top
Bank *Pipeline
*Pipeline
*Pipeline
Multiplier
Register
Register
Register
Bottom
Multiplier
fp32_chainout[31:0]
*This block diagram shows the functional representation of the DSP block.
The pipeline registers are embedded within the various circuits of the DSP block.
Output
Register
Bank
Adder
Register
fp32_chainout[31:0]
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
fp32_result[31:0]
Result Real
fp16_mult_top_invalid
fp16_mult_top_inexact
fp16_mult_top_overflow
fp16_mult_top_underflow
fp16_mult_top_infinite(extended mode)
fp16_mult_top_zero(extended mode)
fp16_mult_bot_invalid
fp16_mult_bot_inexact
fp16_mult_bot_overflow
fp16_mult_bot_underflow
fp16_mult_bot_infinite(extended mode)
fp16_mult_bot_zero(extended mode)
fp16_adder_invalid
fp16_adder_inexact
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