Intel Agilex User Manual page 71

4. Intel Agilex Variable Precision DSP Blocks Design Considerations
UG-20213 | 2019.04.02
Table 34. Supported Register Configurations For Sum of Two FP16 Multiplication with
Accumulation Mode
Latency Data Input
Register
accumul fp16_mu
ate_clke lt_input
n _clken
1 Disable Disable
2 Enable Enable
≥3 Enable Enable
≥4 Enable Enable
≥5 Enable Enable
Table 35. Supported Register Configurations For FP16 Vector One Mode
Latency Data Input Register
fp32_add
er_a_clke
n
0 Disable
1 Enable
1 Disable
2 Enable
≥3 Enable
≥4 Enable
≥5 Enable
Table 36. Supported Register Configurations For FP16 Vector Two Mode
Latency Data Input Register
fp32_add
er_a_clke
n
0 Disable
1 Enable
Send Feedback
Adder Adder
1st 2nd
Pipeline Pipeline
Register Register
accum_p accum_2
ipeline_c nd_pipel
lken ine_clke
n
Disable Disable
Disable Disable
Disable, Disable,
enable enable
Disable, Disable,
enable enable
Disable, Disable,
enable enable
Adder 1st Adder
Pipeline 2nd
Register Pipeline
Register
fp16_mul fp32_add fp32_add
t_input_c er_a_chai er_a_chai
lken nin_pl_cl nin_2nd_
ken pl_clken
Disable Disable Disable
Enable Disable Disable
Disable Disable Disable
Enable Disable Disable
Enable Disable, Disable,
enable enable
Enable Disable, Disable,
enable enable
Enable Disable, Disable,
enable enable
Adder 1st Adder
Pipeline 2nd
Register Pipeline
Register
fp16_mul fp32_add fp32_add
t_input_c er_a_chai er_a_chai
lken nin_pl_cl nin_2nd_
ken pl_clken
Disable Disable Disable
Enable Disable Disable
Multiplie Multiplie Adder Input
r 1st r 2nd Register
Pipeline Pipeline
Register Register
mult_pip mult_2n accum_a
eline_clk d_pipeli dder_clk
en ne_clken en
Disable Disable Disable
Disable Disable Disable
Disable Disable Enable
Disable Disable Enable
Disable, Enable Enable
enable
Multiplier Multiplier
1st 2nd
Pipeline Pipeline
Register Register
mult_pipe mult_2nd
line_clke _pipeline
n _clken
Disable Disable
Disable Disable
Disable Disable
Disable Disable
Disable Disable
Disable Disable
Disable, Disable,
enable enable
Multiplier Multiplier
1st 2nd
Pipeline Pipeline
Register Register
mult_pipe mult_2nd
line_clke _pipeline
n _clken
Disable Disable
Disable Disable
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
Adder Output
Pipeline Register
Register
adder_in adder_pl output_c
put_clke _clken lken
n
Disable Disable Enable
Disable Disable Enable
Enable Disable Enable
Enable Enable Enable
Enable Enable Enable
Adder Adder Output
Input Pipeline Register
Register Register
adder_inp adder_pl_ output_cl
ut_clken clken ken
Disable Disable Disable
Disable Disable Disable
Disable Disable Enable
Disable Disable Enable
Enable Disable Enable
Enable Enable Enable
Enable Enable Enable
Adder Adder Output
Input Pipeline Register
Register Register
adder_inp adder_pl_ output_cl
ut_clken clken ken
Disable Disable Disable
Disable Disable Disable
continued...
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