Intel Agilex User Manual page 70

4.2.1.2. FP16 Operation Mode Supported Register Configurations
Table 32. Supported Register Configurations For Sum of Two FP16 Multiplication Mode
Latency Data Input
Register
fp16_mult_inp
ut_clken
0 Disable
1 Enable
1 Disable
2 Enable
3 Enable
4 Enable
≥5 Enable
Table 33. Supported Register Configurations For Sum of Two FP16 Multiplication with
FP32 Addition Mode
Latency Data Input Register
fp32_add
er_a_clke
n
0 Disable
1 Enable
1 Disable
2 Enable
≥3 Enable
≥4 Enable
≥5 Enable
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
70
4. Intel Agilex Variable Precision DSP Blocks Design Considerations
Multiplier 1st Multiplier 2nd
Pipeline
Register
mult_pipeline mult_2nd_pip
_clken
Disable Disable
Disable Disable
Disable Disable
Disable Disable
Disable Disable
Disable Disable
Disable, enable Enable
Adder 1st Adder
Pipeline 2nd
Register Pipeline
Register
fp16_mul fp32_add fp32_add
t_input_c er_a_chai er_a_chai
lken nin_pl_cl nin_2nd_
ken pl_clken
Disable Disable Disable
Enable Disable Disable
Disable Disable Disable
Enable Disable Disable
Enable Disable, Disable,
enable enable
Enable Disable, Disable,
enable enable
Enable Disable, Disable,
enable enable
Adder Input
Pipeline Register
Register
adder_input_c
eline_clken lken
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Multiplier Multiplier
1st 2nd
Pipeline Pipeline
Register Register
mult_pipe mult_2nd
line_clke _pipeline
n _clken
Disable Disable
Disable Disable
Disable Disable
Disable Disable
Disable Disable
Disable Disable
Disable, Enable
enable
UG-20213 | 2019.04.02
Adder Pipeline Output
Register Register
adder_pl_clke output_clken
n
Disable Disable
Disable Disable
Enable
Enable
Disable Enable
Enable Enable
Enable Enable
Adder Adder Output
Input Pipeline Register
Register Register
adder_inp adder_pl_ output_cl
ut_clken clken ken
Disable Disable Disable
Disable Disable Disable
Disable Disable Enable
Disable Disable Enable
Enable Disable Enable
Enable Enable Enable
Enable Enable Enable
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