Intel Agilex User Manual page 57

3. Intel Agilex Variable Precision DSP Blocks Operational Modes
UG-20213 | 2019.04.02
Figure 40. Direct Vector Dot Product Using FP32 Single-Precision Floating-Point
Arithmetic
Connect this signal to
the fp32_chainout signal
of the next DSP block in chain.
IJ +KL + MN + OP
AB + CD + EF + GH
AB + CD
For FP16 half-precision floating-point arithmetic, the direct vector dot product consists
of:
• Sum of two multiplication with FP32 addition mode with chainin feature enabled
• Vector one
• Vector two
Send Feedback
fp32_chainin[31:0]
accumulate
Input
fp32_adder_a[31:0]
Register
Bank
fp32_adder_b[31:0]
J fp32_mult_a[31:0]
*Pipeline *Pipeline
Register Register
I fp32_mult_b[31:0]
Bank
Multiplier
Vector One
fp32_chainin[31:0]
accumulate
Input
fp32_adder_a[31:0]
Register
Bank
fp32_adder_b[31:0]
fp32_mult_a[31:0]
H
*Pipeline
Register
G fp32_mult_b[31:0]
Bank
Multiplier
Vector Two
fp32_chainin[31:0]
accumulate
Input
fp32_adder_a[31:0]
EF + GH Register
Bank
fp32_adder_b[31:0]
F fp32_mult_a[31:0]
*Pipeline *Pipeline
Register Register
E
fp32_mult_b[31:0]
Bank
Multiplier
Vector One
fp32_chainin[31:0]
accumulate
Input
fp32_adder_a[31:0]
Register
Bank
fp32_adder_b[31:0]
D fp32_mult_a[31:0]
*Pipeline
Register
fp32_mult_b[31:0]
C
Bank
Multiplier
Vector Two
fp32_chainin[31:0]
accumulate
Input
fp32_adder_a[31:0]
Register
Bank
fp32_adder_b[31:0]
B fp32_mult_a[31:0]
*Pipeline *Pipeline
Register
A fp32_mult_b[31:0]
Bank
Multiplier
Multiply Add
*This block diagram shows the functional representation of the DSP block.
The pipeline registers are embedded within the various circuits of the DSP block.
*Pipeline *Pipeline
Register Register
*Pipeline
Bank Bank
Adder
Register
Bank
Bank
fp32_chainout[31:0]
*Pipeline *Pipeline
Register Register
*Pipeline
Bank Bank
Adder
Register
Bank
*Pipeline
Register
Bank
fp32_chainout[31:0]
*Pipeline *Pipeline
Register Register
*Pipeline
Bank Bank
Adder
Register
Bank
Bank
fp32_chainout[31:0]
*Pipeline *Pipeline
Register Register
*Pipeline
Bank Bank
Adder
Register
Bank
*Pipeline
Register
Bank
fp32_chainout[31:0]
*Pipeline *Pipeline
Register Register
*Pipeline
Bank Bank
Adder
Register
Bank
Register
Bank
fp32_chainout[31:0]
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
Output
fp32_result[31:0] IJ +KL
Register
Bank fp32_mult_invalid
fp32_mult_inexact
fp32_mult_overflow
fp32_mult_underflow
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
Output
fp32_result[31:0] AB + CD +EF + GH + IJ +KL
Register
Bank
fp32_mult_invalid
fp32_mult_inexact
fp32_mult_overflow
fp32_mult_underflow
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
Output
fp32_result[31:0] EF + GH
Register
fp32_mult_invalid
Bank
fp32_mult_inexact
fp32_mult_overflow
fp32_mult_underflow
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
Output
fp32_result[31:0] AB + CD + EF + GH
Register
Bank
fp32_mult_invalid
fp32_mult_inexact
fp32_mult_overflow
fp32_mult_underflow
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
Output
fp32_result[31:0] AB + CD
Register
fp32_mult_invalid
Bank
fp32_mult_inexact
fp32_mult_overflow
fp32_mult_underflow
fp32_adder_invalid
fp32_adder_inexact
fp32_dder_overflow
fp32_adder_underflow
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