Intel Agilex User Manual page 11

2. Intel Agilex Variable Precision DSP Blocks Architecture
UG-20213 | 2019.04.02
Figure 2. Fixed-Point Arithmetic 18 x 19 Mode
DISABLE_CHAINOUT
DISABLE_SCANIN
LOADCONST
ACCUMULATE
NEGATE
ay[18..0]
az[17..0]
ax[17..0]
COEFSELA[2..0]
by[18..0]
bz[17..0]
bx[17..0]
COEFSELB[2..0]
Figure 3. Fixed-Point Arithmetic 27 x 27 Mode
DISABLE_CHAINOUT
LOADCONST
ACCUMULATE
NEGATE
ay[26:0]
az[25:0]
ax[26:0]
COEFSELA[2:0]
Send Feedback
scanin[18..0]
SUB
Pre-Adder
0
1
+/-
Internal
Coefficient
Top delay
register
Pre-Adder
+/-
Internal
Coefficient
scanout[18..0]
*This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.
**Systolic registers are enabled in systolic mode only.
scanin[26:0]
Input
*1st *2nd
Register
Pipeline Pipeline
Bank
Register Register
Internal
Coefficients
scanout[26:0]
*This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.
chainin[63..0]
CLK
ENA[2..0]
CLR[1..0]
**Systolic
**Systolic
Registers Multiplier
Register
x
+/- +/-
+/-
**Systolic
Chainout adder/
Adder
Registers
and Subtractor
Multiplier
x
64'b0
1 0
chainout[63..0]
clk
chainin[63:0]
ena[2:0]
clr [1:0]
Pre-Adder
+/- Chainout Adder/
Accumulator
Multiplier
+
x
+/-
64'b0
1 0
chainout[63:0]
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
Constant
+
Double
Accumulation
accumulator
Register
resulta[36:0]
resultb[36:0]
Constant
Double
Accumulation
Register
Output
resulta[63:0]
64
Register
Bank
11