Intel Agilex User Manual page 50

3.2.2.5. FP16 Vector One Mode
This mode performs a summation of two half-precision multiplications with the chainin
input from the previous variable DSP Block. The output is a single-precision floating-
point value which is fed into chainout.
Table 19. Equations Applied to FP16 Vector One Mode
Chainin Parameter
Disable
Enable
The following are exception flags supported in flushed and bfloat16 formats:
•
fp16_mult_top_invalid
•
fp16_mult_top_inexact
•
fp16_mult_top_overflow
•
fp16_mult_top_underflow
•
fp16_mult_bot_invalid
•
fp16_mult_bot_inexact
•
fp16_mult_bot_overflow
•
fp16_mult_bot_underflow
•
fp16_adder_invalid
•
fp16_adder_inexact
•
fp16_adder_overflow
•
fp16_adder_underflow
•
fp32_adder_invalid
•
fp32_adder_inexact
•
fp32_adder_overflow
•
fp32_adder_underflow
The following are exception flags supported in extended format:
•
fp16_mult_top_invalid
•
fp16_mult_top_inexact
•
fp16_mult_top_infinite
•
fp16_mult_top_zero
•
fp16_mult_bot_invalid
•
fp16_mult_bot_inexact
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
50
3. Intel Agilex Variable Precision DSP Blocks Operational Modes
Vector One with Floating-Point
Addition
fp32_result = (fp16_mult_top_a *
fp16_mult_top_b) + (fp16_mult_bot_a
* fp16_mult_bot_b)
Chainout = fp32_adder_a
fp32_result = (fp16_mult_top_a *
fp16_mult_top_b) + (fp16_mult_bot_a
* fp16_mult_bot_b) + fp32_chainin
Chainout = fp32_adder_a
UG-20213 | 2019.04.02
Vector One with Floating-Point
Subtraction
fp32_result = (fp16_mult_top_a *
fp16_mult_top_b) - (fp16_mult_bot_a
* fp16_mult_bot_b)
Chainout = fp32_adder_a
fp32_result = (fp16_mult_top_a *
fp16_mult_top_b) - (fp16_mult_bot_a
* fp16_mult_bot_b) - fp32_chainin
Chainout = fp32_adder_a
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