Intel Agilex User Manual page 13

2. Intel Agilex Variable Precision DSP Blocks Architecture
UG-20213 | 2019.04.02
• Data
• Dynamic control signals
— NEGATE
— LOADCONST
— ACCUMULATE
— SUB
— Dynamic Scanin
— Dynamic Chainout
All the registers in the DSP blocks are positive-edge triggered and cleared on power
up. Each multiplier operand can feed an input register or a multiplier directly,
bypassing the input registers.
The following variable precision DSP block signals control the input registers within the
variable precision DSP block:
•
CLK
•
ENA[2..0]
•
CLR[0]
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Intel Agilex Variable Precision DSP Blocks User Guide
13