Intel Agilex User Manual page 59

3. Intel Agilex Variable Precision DSP Blocks Operational Modes
UG-20213 | 2019.04.02
The imaginary part [(a × d) + (b × c)] is implemented in the first two variable-
precision DSP blocks, while the real part [(a × c) - (b × d)] is implemented in the next
two variable-precision DSP blocks.
Figure 43. Complex Multiplication with Imaginary Result Using FP32 Single-Precision
Floating-Point Arithmetic
fp32_chainin[31:0]
accumulate
fp32_adder_a[31:0]
fp32_adder_b[31:0]
a
fp32_mult_b[31:0]
d fp32_mult_b31:0]
accumulate
fp32_adder_a[31:0]
fp32_adder_b[31:0]
b fp32_mult_a[31:0]
c fp32_mult_b[31:0]
Send Feedback
*Pipeline
Register
Input
Register
Bank
*Pipeline *Pipeline
Register Register
Multiplier Bank Bank
Multiplication Mode
fp32_chainout[31:0]
fp32_chainin[31:0]
Input
Register
Bank
*Pipeline *Pipeline
Register Register
Bank Bank
Multiplier
Multiply-Add Mode
*This block diagram shows the functional representation of the DSP block.
The pipeline registers are embedded within the various circuits of the DSP block.
*Pipeline
Register
*Pipeline
Bank Bank
Adder
Register
Bank
*Pipeline *Pipeline
Register Register
*Pipeline
Bank Bank
Adder
Register
Bank
fp32_chainout[31:0]
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
Output
fp32_result[31:0]
Register
fp32_mult_invalid
Bank
fp32_mult_inexact
fp32_mult_overflow
fp32_mult_underflow
Output
fp32_result[31:0]
Register Result Imaginary
Bank fp32_mult_invalid
fp32_mult_inexact
fp32_mult_overflow
fp32_mult_underflow
fp32_adder_invalid
fp32_adder_inexact
fp32_dder_overflow
fp32_adder_underflow
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