Intel Agilex User Manual page 53

3. Intel Agilex Variable Precision DSP Blocks Operational Modes
UG-20213 | 2019.04.02
•
fp32_adder_inexact
•
fp32_adder_overflow
•
fp32_adder_underflow
Figure 37. FP16 Vector Two Mode
fp32_chainin[31:0]
fp32_adder_a[31:0]
fp16_mult_top_a[15:0]
fp16_mult_top_b[15:0]
fp16_mult_bot_a[15:0]
fp16_mult_bot_b[15:0]
3.2.2.7. FP16 Vector Three Mode
This mode performs a single-precision accumulation and a summation of two half-
precision multiplications.
Table 21. Equations Applied to Vector Three Mode
Accumulate Input
Disable
Enable
The following are exception flags supported in flushed and bfloat16 formats:
•
fp16_mult_top_invalid
•
fp16_mult_top_inexact
•
fp16_mult_top_overflow
•
fp16_mult_top_underflow
•
fp16_mult_bot_invalid
Send Feedback
Input
Register
Bank
Top
*Pipeline
*Pipeline
Multiplier
Register
Register
Bottom
Multiplier
*This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.
Vector Three with Floating-Point
fp32_result =
fp32_adder_a
fp32_chainout = {
*
fp16_mult_top_b
{
fp16_mult_bot_a
fp16_mult_bot_b
fp32_result =
fp32_adder_a
fp32_result(t-1)
fp32_chainout = {
*
fp16_mult_top_b
{
fp16_mult_bot_a
fp16_mult_bot_b
*Pipeline *Pipeline
*Pipeline
Register Register
Register
Adder
Adder
*Pipeline Register
Register
fp32_chainout[31:0]
Vector Three with Floating-Point
Addition
fp32_result =
fp32_chainout = {
fp16_mult_top_a
} + *
fp16_mult_top_b
* {
fp16_mult_bot_a
}
fp16_mult_bot_b
+ fp32_result =
fp32_result(t-1)
fp32_chainout = {
fp16_mult_top_a
} + *
fp16_mult_top_b
* {
fp16_mult_bot_a
}
fp16_mult_bot_b
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
Output fp32_result[31:0]
Register fp16_mult_top_invalid
fp16_mult_top_inexact
Bank
fp16_mult_top_overflow
fp16_mult_top_underflow
fp16_mult_top_infinite(extended format)
fp16_mult_top_zero(extended format)
fp16_mult_bot_invalid
fp16_mult_bot_inexact
fp16_mult_bot_overflow
fp16_mult_bot_underflow
fp16_mult_bot_infinite(extended format)
fp16_mult_bot_zero(extended format)
fp16_adder_invalid
fp16_adder_inexact
fp16_adder_overflow
fp16_adder_underflow
fp16_adder_infinite(extended format)
fp16_adder_zero(extended format)
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
Subtraction
fp32_adder_a
fp16_mult_top_a
} -
*
}
-
fp32_adder_a
fp16_mult_top_a
} -
*
}
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