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•
PSO—Sets the MAX V PSO register. The following options are available:
— Use PSR—Allows the PSR to determine the page of flash memory to use for
FPGA reconfiguration.
— Use PSS—Allows the PSS to determine the page of flash memory to use for
FPGA reconfiguration.
•
PSR—Sets the MAX V PSR register. The numerical value in the list corresponds to
the page of flash memory to load during FPGA reconfiguration. Refer to the MAX V
Registers table above for more information.
•
PSS—Displays the MAX V PSS register value. Refer to MAX V Registers table for
the list of available options.
•
SRST—Resets the system and reloads the FPGA with a design from flash memory
based on the other MAX V register values. Refer to MAX V Registers table for more
information.
As the System Info tab requires that a specific design is running in the FPGA at a
specific clock speed, writing a 0 to SRST or changing the PSO value can cause the
Board Test System to stop running.
6.3.2.5. JTAG Chain
This control shows all the devices currently in the JTAG chain. The Cyclone V GT
device is always the first device in the chain. The JTAG chain is normally mastered by
the On-board Intel FPGA Download Cable II.
If you plug in an external download cable to the JTAG header (J13), the On-Board
Intel FPGA Download Cable II is disabled.
JTAG DIP switch bank (SW3) selects which interfaces are in the chain. Refer to
on page 13 table for detailed settings.
For details on the JTAG chain, refer to the Cyclone V GT FPGA Development Board
Reference Manual. For Intel FPGA Download Cable II configuration details, refer to the
On-Board Intel FPGA Download Cable II User Guide page.
Related Information
•
Cyclone V GT FPGA Development Board Reference Manual
•
Intel FPGA Download Cable II User Guide
6.3.3. The GPIO Tab
The GPIO tab allows you to interact with all the general purpose user I/O components
on your board. You can write to the character LCD, read DIP switch settings, turn LEDs
on or off, and detect push button presses. The following figure shows the GPIO tab.
®
Cyclone
V GT FPGA Development Kit User Guide
26
6. Board Test System
792833 | 2024.02.21
Table 3
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