Status Register Sets; Register Bit Descriptions; Standard Event Register; Figure 14-4 Standard Event Status - Keithley 2500 User Manual

Models 2500 and 2502 User's Manual

Status register sets

As shown in
Model 2500: Standard Event Status, Operation Event Status, Measurement Event Status,
and Questionable Event Status.
NOTE

Register bit descriptions

Standard event register

The used bits of the standard event register (shown in
follows:
Figure 14-4
Standard event status
*ESR?
OR
To Event
*ESE
Summary Bit
*ESE?
(ESB) of Status
Byte Register
(Figure 14-3)
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Figure 14-1, there are four status register sets in the status structure of the
See Appendix B for details on which register bits are set by specific error and
status conditions.
— PON URQ
(B15 - B8) (B7) (B6)
&
&
— PON URQ
(B15 - B8) (B7) (B6)
PON = Power On
URQ = User Request
CME = Command Error
EXE = Execution Error
Figure
CME EXE DDE QYE
(B5) (B4) (B3) (B2)
&
&
&
&
CME EXE DDE QYE
(B5) (B4) (B3) (B2)
DDE = Device-Dependent Error
QYE = Query Error
OPC = Operation Complete
& = Logical AND
OR = Logical OR
Status Structure 14-11
14-4) are described as
Standard
— OPC
Event Status
(B1) (B0)
Register
&
Standard
Event Status
— OPC
Enable
(B1) (B0)
Register