Processor Clock Control Register Format - NEC PD78052 User Manual

Symbol <7> <6> <5>
PCC MCC FRC CLS
R/W
CSS PCC2 PCC1 PCC0
0 0
0 0
0 0 1
0 1
1 0
0 0
0 0
1 0 1
0 1
1 0
Other than above
CPU Clock Status
R CLS
0 Main system clock
1 Subsystem clock
FRC Subsystem Clock Feedback Resistor Selection
R/W
0 Internal feedback resistor used
1 Internal feedback resistor not used
Main System Clock Oscillation Control
R/W MCC
0 Oscillation possible
1 Oscillation stopped
Notes 1. Bit 5 is Read Only.
2. When the CPU is operating on the subsystem clock, MCC should be used to stop the main
system clock oscillation. A STOP instruction should not be used.
Caution Bit 3 must be set to 0.
Remarks 1. f
XX
2. f
X
3. f
XT
4. MCS : Bit 0 of oscillation mode selection register (OSMS)
162
CHAPTER 7 CLOCK GENERATOR
Figure 7-3. Processor Clock Control Register Format
<4> 3 2 1
CSS 0 PCC2 PCC1 PCC0
CPU CIock (f ) Selection
CPU
MCS = 1
0
f f
XX x
1 f /2 f /2
XX x
2 2
f /2 f /2
0
XX x
3 3
1 f /2 f /2
XX x
4 4
0 f /2 f /2
XX x
0
1
f /2
0
XT
1
0
Setting prohibited
Note 2
: Main system clock frequency (f
: Main system clock oscillator frequency
: Subsystem clock oscillator frequency
After
0 Address Reset
FFFBH 04H
MCS = 0
f
x
f
x
f
x
f
x
f
x
or f /2)
X X
R/W
Note 1
R/W
/2
2
/2
3
/2
4
/2
5
/2