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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries)
Symbol
7
6
5
TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30
TCL33 TCL32 TCL31 TCL30
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
Other than above
TCL37 TCL36 TCL35 TCL34
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
Other than above
Caution When rewriting TCL3 to other data, stop the serial transfer operation beforehand.
Remarks 1. f
XX
2. f
X
3. MCS : Bit 0 of oscillation mode selection register (OSMS)
4. Figures in parentheses apply to operation with f
Figure 16-3. Timer Clock Select Register 3 Format
4
3
2
1
0
Serial Interface Channel 0 Serial Clock Selection
MCS = 1
0
f
/2
Setting prohibited
XX
1
f
/2
2
f
/2
2
(1.25 MHz)
XX
X
0
f
/2
3
f
/2
3
(625 kHz)
XX
X
1
f
/2
f
/2
(313 kHz)
4
4
XX
X
0
f
/2
f
/2
(156 kHz)
5
5
XX
X
1
f
/2
6
f
/2
6
(78.1 kHz)
XX
X
0
f
/2
7
f
/2
7
(39.1 kHz)
XX
X
1
f
/2
8
f
/2
8
(19.5 kHz)
XX
X
Setting prohibited
Serial Interface Channel 1 Serial Clock Selection
MCS = 1
0
f
/2
Setting prohibited
XX
1
f
/2
2
f
/2
2
(1.25 MHz)
XX
X
0
f
/2
3
f
/2
3
(625 kHz)
XX
X
1
f
/2
4
f
/2
4
(313 kHz)
XX
X
0
f
/2
5
f
/2
5
(156 kHz)
XX
X
1
f
/2
6
f
/2
6
(78.1 kHz)
XX
X
0
f
/2
7
f
/2
7
(39.1 kHz)
XX
X
1
f
/2
8
f
/2
8
(19.5 kHz)
XX
X
Setting prohibited
: Main system clock frequency (f
: Main system clock oscillation frequency
Address
After Reset
R/W
FF43H
88H
R/W
MCS = 0
f
/2
2
(1.25 MHz)
X
f
/2
3
(625 kHz)
X
f
/2
4
(313 kHz)
X
f
/2
(156 kHz)
5
X
f
/2
(78.1 kHz)
6
X
f
/2
7
(39.1 kHz)
X
f
/2
8
(19.5 kHz)
X
f
/2
9
(9.8 kHz)
X
MCS = 0
f
/2
2
(1.25 MHz)
X
f
/2
3
(625 kHz)
X
f
/2
4
(313 kHz)
X
f
/2
5
(156 kHz)
X
f
/2
6
(78.1 kHz)
X
f
/2
7
(39.1 kHz)
X
f
/2
8
(19.5 kHz)
X
f
/2
9
(9.8 kHz)
X
or f
/2)
X
X
= 5.0 MHz.
X
295
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