Processor Clock Control Register Format - NEC PD78076 User Manual

Symbol <7> <6> <5>
PCC MCC FRC CLS
R/W CSS PCC2 PCC1 PCC0
0 0
0 0
0 0 1
0 1
1 0
0 0
0 0
1 0 1
0 1
1 0
Other than above
CLS CPU Clock Status
R
0 Main system clock
1 Subsystem clock
Subsystem Clock Feedback Resistor Selection
FRC
R/W
0 Internal feedback resistor used
1 Internal feedback resistor not used
R/W MCC Main System Clock Oscillation Control
0 Oscillation possible
1 Oscillation stopped
Notes 1. Bit 5 is a read-only bit.
2. When the CPU is operating on the subsystem clock, MCC should be used to stop the main
system clock oscillation. A STOP instruction should not be used.
Caution Bit 3 must be set to 0.
Remarks 1. f
XX
2. f
X
3. f
XT
4. MCS : Bit 0 of oscillation mode selection register (OSMS)
168
CHAPTER 7 CLOCK GENERATOR
Figure 7-3. Processor Clock Control Register Format
<4> 3 2 1
CSS 0 PCC2 PCC1 PCC0
CPU CIock (f ) Selection
CPU
MCS = 1
0 f f
XX X
1 f /2
f /2
XX
X
2
0 f /2
f /2
XX
X
3
f /2
1
XX f /2
X
4
0 f /2
XX f /2
X
0
1
0
f /2
XT
1
0
Setting prohibited
Note 2
: Main system clock frequency (f
: Main system clock oscillation frequency
: Subsystem clock oscillation frequency
After
0 Address Reset
FFFBH 04H
2
3
4
or f /2)
X X
R/W
Note 1
R/W
MCS = 0
f /2
X
2
f /2
X
3
f /2
X
4
f /2
X
5
f /2
X