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5.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the
immediate data of an operation code are transferred to the program counter (PC) and branched.
Before the CALLT [addr5] instruction is executed, table indirect addressing is performed. This instruction
references an address stored in the memory table at addresses 40H through 7FH, and can branch in the entire
memory space.
[Illustration]
Operation Code
Effective Address
Effective Address+1
5.3.4 Register addressing
[Function]
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)
and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
rp
PC
120
CHAPTER 5 CPU ARCHITECTURE
7
6
5
1
1
ta
4–0
15
0
0
0
0
0
7
Memory (Table)
Low Addr.
High Addr.
15
PC
7
0
A
15
8
1
0
1
8
7
6
5
0
0
0
0
1
0
8
7
7
X
7
1
0
0
0
0
0
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