Slave Wait Release (Reception) - NEC PD78052 User Manual

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries)
(3) Slave wait release (slave reception)
The slave is released from the wait status when the WREL flag (bit 2 of the interrupt timing specify register
(SINT)) is set or when an instruction that writes data to the serial I/O shift register 0 (SIO0) is executed.
When the slave receives data, the first bit of the data sent from the master may not be received if the SCL
line immediately goes into a high-impedance state after an instruction that writes data to SIO has been
executed.
This is because SIO0 does not start operating if the SCL line is in the high-impedance state while the
instruction that writes data to SIO0 is executed (until the next instruction is executed).
Therefore, receive the data by manipulating the output latch of P27 by program, as shown in Figure 17-26.
For this timing, refer to Figure 17-22.
Master device operation
Software operation
Hardware operation
Transfer line
SCL
SDA0 (SDA1) A0
Slave device operation
Software operation
Hardware operation
Figure 17-26. Slave Wait Release (Reception)
Writing
data to
SIO0
Setting Setting
ACKD CSIIF0
9
W ACK
ACK Setting
output CSIIF0
Serial transmission
1 2
D7
P27 Write P27
output FFH output
latch 0 to SIO0 latch 1
Wait
release
3
D6 D5
Serial reception
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