Bit Timer Mode Control Register Format - NEC PD78052 User Manual

Figure 8-4. 16-Bit Timer Mode Control Register Format
Symbol 7 6 5
TMC0 0 0 0
OVF0 16-Bit Timer Register Overflow Detection
0 Overflow not detected
1 Overflow detected
TMC03 TMC02 TMC01
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Remarks 1. TO0
2. TI00
3. TM0
4. CR00 : Compare register 00
5. CR01 : Compare register 01
Cautions 1. Switch the clear mode and the T00 output timing after stopping the timer operation
(by setting TMC01 to TMC03 to 0, 0, 0).
2. Set the valid edge of the TI00/INTP0 pin with an external interrupt mode register 0
(INTM0) and select the sampling clock frequency with a sampling clock select register
(SCS).
3. When using the PWM mode, set the PWM mode and then set data to CR00.
4. If clear & start mode on match between TM0 and CR00 is selected, when the set value
of CR00 is FFFFH and the TM0 value changes from FFFFH to 0000H, OVF0 flag is set
to 1.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER
4 3 2 1 <0>
0 TMC03 TMC02 TMC01 OVF0
Operating Mode
Clear Mode Selection
Operation stop
(TM0 cleared to 0)
PWM mode
(free running)
Free running mode
Clear & start on TI00
valid edge
Clear & start on match
between TM0 and CR00
: 16-bit timer/event counter output pin
: 16-bit timer/event counter input pin
: 16-bit timer register
Address After Reset
FF48H 00H
TO0 Output Timing Selection
No change
PWM pulse output
Match between TM0 and
CR00 or match between
TM0 and CR01
Match between TM0 and
CR00, match between
TM0 and CR01 or TI00
valid edge
Match between TM0 and
CR00 or match between
TM0 and CR01
Match between TM0 and
CR00, match between
TM0 and CR01 or TI00
valid edge
Match between TM0 and
CR00 or match between
TM0 and CR01
Match between TM0 and
CR00, match between
TM0 and CR01 or TI00
valid edge
R/W
R/W
Interrupt Generation
Not Generated
Generated on match
between TM0 and CR00,
or match between TM0
and CR01
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