NEC PD78052 User Manual page 316

CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries)
(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SBIC to 00H.
The shaded area is used in the SBI mode.
Symbol
<7> <6> <5>
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
Used for bus release signal output.
When RELT = 1, SO0 Iatch is set to (1). After SO0 latch setting, automatically cleared to (0).
RELT
Also cleared to 0 when CSIE0 = 0.
R/W
Used for command signal output.
When CMDT = 1, SO0 Iatch is cleared to (0). After SO0 latch clearance, automatically cleared to (0).
CMDT
Also cleared to 0 when CSIE0 = 0.
R RELD Bus Release Detection
Clear Conditions (RELD = 0)
• When transfer start instruction is executed
• If SIO0 and SVA values do not match in address
reception (only when WUP = 1)
• When CSIE0 = 0
• When RESET input is applied
R CMDD Command Detection
Clear Conditions (CMDD = 0)
• When transfer start instruction is executed
• When bus release signal (REL) is detected
• When CSIE0 = 0
• When RESET input is applied
R/W
Acknowledge signal is output in synchronization with the falling edge clock of SCK0 just after execution
of the instruction to be set to (1) and, after acknowledge signal output, automatically cleared to (0).
ACKT
Used as ACKE=0. Also cleared to (0) upon start of serial interface transfer or when CSIE0 = 0.
R/W
ACKE Acknowledge Signal Automatic Output Control
0 Acknowledge signal automatic output disable (output with ACKT enable)
Before completion of
transfer
1
After completion of
transfer
Note Bits 2, 3, and 6 (RELD, CMDD and ACKD) are read-only bits.
Remarks 1. Bits 0, 1, and 4 (RELT, CMDT, and ACKT) are 0 when read after data setting.
2. CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)
316
<4> <3> <2> <1> <0>
Acknowledge signal is output in synchronization with the 9th clock falling edge of
SCK0 (automatically output when ACKE = 1).
Acknowledge signal is output in synchronization with falling edge clock
of SCK0 just after execution of the instruction to be set to 1
(automatically output when ACKE = 1).
However, not automatically cleared to 0 after acknowledge signal output.
Address After Reset R/W
FF61H 00H R/W Note
Set Conditions (RELD = 1)
• When bus release signal (REL) is detected
Set Conditions (CMDD = 1)
• When command signal (CMD) is detected
(Continued)