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(5) Sampling clock select register (SCS)
This register is used to set the valid edge clock sampling clock to be input to INTP0. When remote controlled
data reception is carried out using INTP0, digital noise is removed with sampling clocks.
SCS is set with an 8-bit memory manipulation instruction.
RESET input sets SCS to 00H.
Symbol
7
6
5
SCS
0
0
0
N
Caution f
/2
is a clock to be supplied to the CPU and f
XX
to the peripheral hardware. f
Remarks 1. N
2. f
XX
3. f
X
4. MCS :
5. Values in parentheses when operated with f
494
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
Figure 21-7. Sampling Clock Select Register Format
4
3
2
1
0
0
0
SCS1
N
/2
XX
:
Value (N=0 to 4) at bits 0 to 2 (PCC0 to PCC2) of processor clock control register
(PCC)
:
Main system clock frequency (f
:
Main system clock oscillation frequency
Oscillation mode selection register (OSMS) bit 0
After
Address
0
Reset
SCS0
FF47H
00H
INTP0 Sampling Clock Selection
SCS1
SCS0
N
0
0
f
/2
xx
7
0
1
f
/2
xx
5
1
0
f
/2
xx
6
1
1
f
/2
xx
5
6
/2
, f
/2
and f
XX
XX
stops in the HALT mode.
or f
/2)
X
X
= 5.0 MHz.
X
R/W
R/W
MCS = 1
MCS = 0
7
8
f
/2
(39.1 kHz)
f
/2
(19.5 kHz)
x
x
5
6
f
/2
(156.3 kHz)
f
/2
(78.1 kHz)
x
x
6
7
f
/2
(78.1 kHz)
f
/2
(39.1 kHz)
x
x
7
/2
are clocks to be supplied
XX
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