Timer Clock Selection Register 0 Format - NEC PD78052 User Manual

Symbol <7> 6 5
CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00
TCL0
TCL03 TCL02 TCL01 TCL00
0 0 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
1 0 1
1 0 1
1 1 0
Other than above
TCL06 TCL05 TCL04
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 1 1
Other than above
PCL Output Control
CLOE
0 Output disabled
1 Output enabled
Cautions 1. The TI00/INTP0 pin valid edge is set by external interrupt mode register 0 (INTM0), and
the sampling clock frequency is selected by the sampling clock selection register
(SCS).
2. When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory
manipulation instruction.
3. To read the count value when TI00 has been specified as the TM0 count clock, the value
should be read from TM0, not from 16-bit capture/compare register 01 (CR01).
4. When rewriting TCL0 to other data, stop the timer operation beforehand.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER
Figure 8-3. Timer Clock Selection Register 0 Format
4 3 2 1 0
PCL Output Clock Selection
MCS = 1
0 f (32.768 kHz)
XT
1 f f (5.0 MHz)
XX X
0 f /2 f /2 (2.5 MHz)
XX X
2 2
1 f /2 f /2 (1.25 MHz)
XX X
3 3
0 f /2 f /2 (625 kHz)
XX X
4 4
1 f /2 f /2 (313 kHz)
XX X
5 5
0 f /2 f /2 (156 kHz)
XX X
6 6
1 f /2 f /2 (78.1 kHz)
XX X
7 7
0 f /2 f /2 (39.1 kHz)
XX X
Setting prohibited
16-Bit Timer Register Count Clock Selection
MCS = 1
TI00 (Valid edge specifiable)
2f Setting prohibited
XX
f f (5.0 MHz)
XX X
f /2 f /2 (2.5 MHz)
XX X
2 2
f /2 f /2 (1.25 MHz)
XX X
Watch timer output (INTTM 3)
Setting prohibited
Address After Reset R/W
FF40H 00H R/W
MCS = 0
f /2 (2.5 MHz)
X
2
f /2 (1.25 MHz)
X
3
f /2 (625 kHz)
X
4
f /2 (313 kHz)
X
5
f /2 (156 kHz)
X
6
f /2 (78.1 kHz)
X
7
f /2 (39.1 kHz)
X
8
f /2 (19.5 kHz)
X
MCS = 0
f (5.0 MHz)
X
f /2 (2.5 MHz)
X
2
f /2 (1.25 MHz)
X
3
f /2 (625 kHz)
X
183