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Symbol
7
7
6
6
5
PCC
MCC
FRC
CLS
R/W
CSS
PCC2
PCC1 PCC0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
1
0
1
0
1
1
0
Other than above
CLS
R
0
Main system clock
1
Subsystem clock
FRC
R/W
0
Internal feedback resistor used
1
Internal feedback resistor not used
R/W
MCC
0
Oscillation possible
1
Oscillation stopped
Notes 1. Bit 5 is Read Only.
2. When the CPU is operating on the subsystem clock, MCC should be used to stop the main
system clock oscillation. A STOP instruction should not be used.
Caution Bit 3 must be set to 0.
Remarks 1. f
XX
2. f
X
3. f
XT
4. MCS : Bit 0 of oscillation mode selection register (OSMS)
158
CHAPTER 7 CLOCK GENERATOR
Figure 7-3. Processor Clock Control Register Format
4
3
2
1
0
CSS
0
PCC2 PCC1 PCC0
0
f
f
XX
x
1
f
/2
f
/2
XX
x
2
2
f
/2
f
/2
0
XX
x
3
3
1
f
/2
f
/2
XX
x
4
4
0
f
/2
f
/2
XX
x
0
1
f
/2
0
XT
1
0
Setting prohibited
Subsystem Clock Feedback Resistor Selection
Main System Clock Oscillation Control
: Main system clock frequency (f
: Main system clock oscillator frequency
: Subsystem clock oscillator frequency
After
Address
Reset
FFFBH
04H
CPU CIock Selection (f
)
CPU
MCS = 1
f
x
f
/2
x
f
/2
x
f
/2
x
f
/2
x
CPU Clock Status
Note 2
or f
/2)
X
X
R/W
Note 1
R/W
MCS = 0
/2
2
3
4
5
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