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Figure No.
19-12.
3-Wire Serial I/O Mode Timing ......................................................................................................
19-13.
Circuit of Switching in Transfer Bit Order ......................................................................................
19-14.
Reception Completion Interrupt Request Generation Timing (when ISRM = 1) ............................
19-15.
Receive Buffer Register Read Disable Period ..............................................................................
20-1.
Real-time Output Port Block Diagram ...........................................................................................
20-2.
Real-time Output Buffer Register Configuration ............................................................................
20-3.
Port Mode Register 12 Format ......................................................................................................
20-4.
Real-time Output Port Mode Register Format ...............................................................................
20-5.
Real-time Output Port Control Register Format ............................................................................
21-1.
Basic Configuration of Interrupt Function ......................................................................................
21-2.
Interrupt Request Flag Register Format ........................................................................................
21-3.
Interrupt Mask Flag Register Format .............................................................................................
21-4.
Priority Specify Flag Register Format ............................................................................................
21-5.
External Interrupt Mode Register 0 Format ...................................................................................
21-6.
External Interrupt Mode Register 1 Format ...................................................................................
21-7.
Sampling Clock Select Register Format ........................................................................................
21-8.
Noise Eliminator Input/Output Timing (during rising edge detection) ............................................
21-9.
Program Status Word Configuration .............................................................................................
21-10.
Flowchart of Generation from Non-Maskable Interrupt Request to Acknowledgment ...................
21-11.
Non-Maskable Interrupt Request Acknowledge Timing .................................................................
21-12.
Non-Maskable Interrupt Request Acknowledge Operation ...........................................................
21-13.
Interrupt Request Acknowledge Processing Algorithm ..................................................................
21-14.
Interrupt Request Acknowledge Timing (Minimum Time) ..............................................................
21-15.
Interrupt Request Acknowledge Timing (Maximum Time) .............................................................
21-16.
Multiple Interrupt Example .............................................................................................................
21-17.
Interrupt Request Hold ..................................................................................................................
21-18.
Basic Configuration of Test Function .............................................................................................
21-19.
Format of Interrupt Request Flag Register 1L ...............................................................................
21-20.
Format of Interrupt Mask Flag Register 1L ....................................................................................
21-21.
Key Return Mode Register Format ................................................................................................
22-1.
Memory Map when Using External Device Expansion Function ...................................................
22-2.
Memory Expansion Mode Register Format ...................................................................................
22-3.
Memory Size Switching Register Format ......................................................................................
22-4.
Instruction Fetch from External Memory .......................................................................................
22-5.
External Memory Read Timing ......................................................................................................
22-6.
External Memory Write Timing ......................................................................................................
22-7.
External Memory Read Modify Write Timing .................................................................................
22-8.
Connection Example of PD78054 and Memory ..........................................................................
23-1.
Oscillation Stabilization Time Select Register Format ...................................................................
23-2.
HALT Mode Clear upon Interrupt Request Generation .................................................................
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