Standby Function Operations; Halt Mode - NEC PD78052 User Manual

23.2 Standby Function Operations

23.2.1 HALT mode

(1) HALT mode set and operating status
The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the
subsystem clock.
The operating status in the HALT mode is described below.
Setting of HALT Mode
Item
Clock generator
CPU
Port (output latch)
16-bit timer/event counter
8-bit timer/event counter
Watch timer
Watchdog timer
A/D converter
D/A converter
Real-time output port
Serial interface Other than
automatic
transmit/
receive
function
Automatic
transmit/
receive
function
External interrupt INTP0
INTP1-INTP6
Bus line for AD0-AD7
external
A0-A15
expansion
ASTB
WR, RD
WAIT
Notes 1. Including when external clock is not supplied
2. Including when external clock is supplied
CHAPTER 23 STANDBY FUNCTION
Table 23-1. HALT Mode Operating Status
On Execution of HALT Instruction during Main
System Clock Operation
Without subsystem With subsystem
Note 1 Note 1
clock clock
Both main system and subsystem clocks can be oscillated. Clock supply to the CPU stops.
Operation stops.
Status before HALT mode setting is held.
Operable.
Operable.
7
Operable when f /2 is Operable.
XX
selected as count clock.
Operable.
Operable.
Operable.
Operable.
Operable.
Operation stops.
INTP0 is operable when clock supplied for peripheral hardware is selected
5 6
as sampling clock (f /2 , f /2 , f
XX XX XX
Operable.
High impedance.
Status before HALT mode setting is held.
Low level.
High level.
High impedance.
On Execution of HALT Instruction during
Subsystem Clock Operation
When main system clock When main system
continues oscillation
Operation stops.
7
/2 ).
clock stops oscillation
Operable when watch
timer output is selected
as count clock (f is
XT
selected as count clock
of watch timer) or when
TI00 is selected.
Operable when TI1 or
TI2 is selected as
count clock.
Operable when f is
XT
selected as count clock.
Operation stops.
Operable when
external SCK is used.
Operation stops.
527