Interrupt Timing Specify Register Format - NEC PD78052 User Manual

CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries)
(4) Interrupt timing specify register (SINT)
This register sets the bus release interrupt and address mask functions and displays the SCK0/P27 pin level
status.
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SINT to 00H.
Symbol
7 <6> <5>
SINT 0 CLD SIC SVAM
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When using wake-up function in the SBI mode, set SIC to 0.
3. When CSIE0 = 0, CLD becomes 0.
Caution Be sure to set bits 0 to 3 to 0.
Remark SVA : Slave address register
CSIIF0 : Interrupt request flag corresponding to INTCSI0
CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)
300
Figure 16-6. Interrupt Timing Specify Register Format
<4> 3 2 1
0 0 0
R/W
R/W
0 Address After Reset
0 FF63H 00H
SVAM SVA Bit to be Used as Slave Address
0 Bits 0 to 7
1 Bits 1 to 7
SIC INTCSI0 Interrupt Cause Selection
CSIIF0 is set upon termination of serial interface
0
channel 0 transfer
CSIIF0 is set upon bus release detection or
1
termination of serial interface channel 0 transfer
R
CLD SCK0/P27 Pin Level
0 Low level
1 High level
R/W
R/W Note 1
Note 2
Note 3