Timer Clock Select Register 0 Format - NEC PD78052 User Manual

<7> 6 5
Symbol
CLOE TCL06 TCL05 TCL04
TCL0
TCL03 TCL02 TCL01
0 0 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
1 0 1
1 0 1
1 1 0
Other than above
TCL06 TCL05 TCL04
0
0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 1 1
Other than above
CLOE PCL Output Control
0 Output disable
1 Output enable
Cautions 1. Set the TI00/P00/INTP0 pin valid edge by external interrupt mode register 0 (INTM0), and
select the sampling clock frequency by the sampling clock selection register (SCS).
2. When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory
manipulation instruction.
3. To read the count value when TI00 has been specified as the TM0 count clock, the value
should be read from TM0, not from 16-bit capture/compare register 01 (CR01).
4. When rewriting TCL0 to other data, stop the clock operation beforehand.
258
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT
Figure 12-3. Timer Clock Select Register 0 Format
4 3 2 1
TCL03 TCL02 TCL01 TCL00
PCL Output Clock Selection
TCL00
MCS = 1
0 f (32.768 kHz)
XT
1 f f (5.0 MHz)
XX X
0 f /2 f /2 (2.5 MHz)
XX X
2 2
1 f /2 f /2 (1.25 MHz)
XX X
3 3
0 f /2 f /2 (625 kHz)
XX X
4 4
1 f /2 f /2 (313 kHz)
XX X
5 5
0 f /2 f /2 (156 kHz)
XX X
6 6
1 f /2 f /2 (78.1 kHz)
XX X
7 7
0 f /2 f /2 (39.1 kHz)
XX X
Setting prohibited
16-Bit Timer Register Count Clock Selection
MCS = 1
TI00 (Valid edge specifiable)
2f Setting prohibited
XX
f f (5.0 MHz)
XX X
f /2 f /2 (2.5 MHz)
XX X
2 2
f /2 f /2 (1.25 MHz)
XX X
Watch Timer Output (INTTM3)
Setting prohibited
After
0 Address
Reset
FF40H 00H
MCS = 0
f
X
f /2 (2.5 MHz)
X
f /2
X
f /2
X
R/W
R/W
MCS = 0
f /2 (2.5 MHz)
X
2
f /2 (1.25 MHz)
X
3
f /2 (625 kHz)
X
4
f /2 (313 kHz)
X
5
f /2 (156 kHz)
X
6
f /2 (78.1 kHz)
X
7
f /2 (39.1 kHz)
X
8
f /2 (19.5 kHz)
X
(5.0 MHz)
2
(1.25 MHz)
3
(625 kHz)