NEC PD78052 User Manual page 299

CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries)
Figure 16-5. Serial Bus Interface Control Register Format (2/2)
R/W
ACKE Acknowledge Signal Automatic Output Control
0 Acknowledge signal automatic output disable (output with ACKT enable)
Before completion of
transfer
1
After completion of
transfer
R
ACKD Acknowledge Detection
Clear Conditions (ACKD = 0)
• Falling edge of the SCK0 immediately after the busy
mode is released while executing the transfer
start instruction
• When CSIE0 = 0
• When RESET input is applied
R/W
Note
BSYE Synchronizing Busy Signal Output Control
Disables busy signal which is output in synchronization with the falling edge of SCK0 clock just after
0
execution of the instruction to be cleared to 0.
1 Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal.
Note The busy mode can be canceled by start of serial interface transfer. However, the BSYE flag is
not cleared to 0.
Remark CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)
Acknowledge signal is output in synchronization with the 9th clock
falling edge of SCK0 (automatically output when ACKE = 1).
Acknowledge signal is output in synchronization with the falling edge of
SCK0 just after execution of the instruction to be set to 1
(automatically output when ACKE = 1).
However, not automatically cleared to 0 after acknowledge signal output.
Set Conditions (ACKD = 1)
• When acknowledge signal (ACK) is detected at the
rising edge of SCK0 clock after completion of
transfer
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