NEC PD78052 User Manual page 570

Instruction
Mnemonic
Group
CALL !addr16
CALLF !addr11
CALLT [addr5]
Call/return
BRK
RET
RETI
RETB
PSW
PUSH
rp
PSW
Stack
POP
manipulate
rp
SP, #word
MOVW SP, AX
AX, SP
!addr16
Uncondi-
tional BR $addr16
branch
AX
BC $addr16
BNC $addr16
Conditional
branch
BZ $addr16
BNZ $addr16
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access.
2. When an area except the internal high-speed RAM area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
control register (PCC).
2. This clock cycle applies to internal ROM program.
570
CHAPTER 27 INSTRUCTION SET
Clock
Operands Byte
Note 1
3 7
2 5
1 6
1 6
1 6
1 6
1 6
1 2
1 4
1 2
1 4
4 –
2 –
2 –
3 6
2 6
2 8
2 6
2 6
2 6
2 6
Operation
Note 2
(SP – 1) (PC + 3) , (SP – 2)
H
–
PC addr16, SP SP – 2
(SP – 1) (PC + 2) , (SP – 2)
H
– PC 00001, PC
15 – 11
SP SP – 2
(SP – 1) (PC + 1) , (SP – 2)
H
PC (00000000, addr5 + 1),
H
–
PC (00000000, addr5),
L
SP SP – 2
(SP – 1) PSW, (SP – 2)
– (SP – 3) (PC + 1) , PC
L
PC (003EH), SP
L
PC (SP + 1), PC
H L
–
SP SP + 2
PC (SP + 1), PC
H L
– PSW (SP + 2), SP
NMIS 0
PC (SP + 1), PC
H L
–
PSW (SP + 2), SP
– (SP – 1) PSW, SP
(SP – 1) rp , (SP – 2)
H
–
SP SP – 2
– PSW (SP), SP SP + 1
rp (SP + 1), rp
H L
–
SP SP + 2
10 SP word
8 SP AX
8 AX SP
– PC addr16
– PC PC + 2 + jdisp8
– PC A, PC X
H L
– PC PC + 2 + jdisp8 if CY = 1
– PC PC + 2 + jdisp8 if CY = 0
– PC PC + 2 + jdisp8 if Z = 1
– PC PC + 2 + jdisp8 if Z = 0
) selected by the processor clock
CPU
Flag
Z AC CY
(PC + 3) ,
L
(PC + 2) ,
L
addr11,
10 – 0
(PC + 1) ,
L
(PC + 1) ,
H
(003FH),
H
SP – 3, IE 0
(SP),
(SP),
SP + 3, R R R
(SP),
R R R
SP + 3
SP – 1
rp ,
L
R R R
(SP),