Table of Contents
Advertisement
Figure No.
17-26.
Slave Wait Release (Reception) ....................................................................................................
17-27.
SCK0/SCL/P27 Pin Configuration .................................................................................................
17-28.
SCK0/SCL/P27 Pin Configuration .................................................................................................
17-29.
Logic Circuit of SCL Signal ............................................................................................................
18-1.
Serial Interface Channel 1 Block Diagram ....................................................................................
18-2.
Timer Clock Select Register 3 Format ...........................................................................................
18-3.
Serial Operation Mode Register 1 Format .....................................................................................
18-4.
Automatic Data Transmit/Receive Control Register Format ..........................................................
18-5.
Automatic Data Transmit/Receive Interval Specify Register Format .............................................
18-6.
3-Wire Serial I/O Mode Timings ....................................................................................................
18-7.
Circuit of Switching in Transfer Bit Order ......................................................................................
18-8.
Basic Transmission/Reception Mode Operation Timings ..............................................................
18-9.
Basic Transmission/Reception Mode Flowchart ............................................................................
18-10.
Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) ......
18-11.
Basic Transmission Mode Operation Timings ...............................................................................
18-12.
Basic Transmission Mode Flowchart .............................................................................................
18-13.
Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) .....................................
18-14.
Repeat Transmission Mode Operation Timing ..............................................................................
18-15.
Repeat Transmission Mode Flowchart ..........................................................................................
18-16.
Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) ..................................
18-17.
Automatic Transmission/Reception Suspension and Restart ........................................................
18-18.
System Configuration When the Busy Control Option is Used .....................................................
18-19.
Operation Timings when Using Busy Control Option (BUSY0 = 0) ...............................................
18-20.
Busy Signal and Wait Cancel (when BUSY0 = 0) .........................................................................
18-21.
Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0) ................................
18-22.
Operation Timing of the Bit Slippage Detection Function Through the Busy SIgnal
(when BUSY0 = 1) .........................................................................................................................
18-23.
Automatic Data Transmit/Receive Interval ....................................................................................
18-24.
Operation Timing with Automatic Data Transmit/Receive Function Performed by
Internal Clock ................................................................................................................................
19-1.
Serial Interface Channel 2 Block Diagram ....................................................................................
19-2.
Baud Rate Generator Block Diagram ............................................................................................
19-3.
Serial Operating Mode Register 2 Format .....................................................................................
19-4.
Asynchronous Serial Interface Mode Register Format ..................................................................
19-5.
Asynchronous Serial Interface Status Register Format ................................................................
19-6.
Baud Rate Generator Control Register Format .............................................................................
19-7.
Asynchronous Serial Interface Transmit/Receive Data Format .....................................................
19-8.
19-9.
Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing .......
19-10.
Receive Error Timing .....................................................................................................................
19-11.
The State of Receive Buffer Register (RXB) and Whether the Receive Completion
Interrupt Request (INTSR) is Generated .......................................................................................
30
LIST OF FIGURES (6/8)
Title
Page
387
390
390
391
395
398
399
400
401
407
408
417
418
419
421
422
423
425
426
427
429
430
431
432
433
434
435
436
441
442
444
445
447
448
461
463
464
465
466
Hide quick links:
Advertisement
Table of Contents
