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Figure No.
6-18.
P130 and P131 Block Diagram .....................................................................................................
6-19.
Port Mode Register Format ...........................................................................................................
6-20.
Pull-Up Resistor Option Register Format ......................................................................................
6-21.
Memory Expansion Mode Register Format ...................................................................................
6-22.
Key Return Mode Register Format ................................................................................................
7-1.
Block Diagram of Clock Generator ................................................................................................
7-2.
Subsystem Clock Feedback Resistor ............................................................................................
7-3.
Processor Clock Control Register Format .....................................................................................
7-4.
Oscillation Mode Selection Register Format .................................................................................
7-5.
Main System Clock when Writing to OSMS ..................................................................................
7-6.
External Circuit of Main System Clock Oscillator ..........................................................................
7-7.
External Circuit of Subsystem Clock Oscillator .............................................................................
7-8.
Examples of Incorrect Oscillator Connection ................................................................................
7-9.
Main System Clock Stop Function ................................................................................................
7-10.
System Clock and CPU Clock Switching ......................................................................................
8-1.
16-Bit Timer/Event Counter Block Diagram ...................................................................................
8-2.
16-Bit Timer/Event Counter Output Control Circuit Block Diagram ...............................................
8-3.
Timer Clock Selection Register 0 Format ......................................................................................
8-4.
16-Bit Timer Mode Control Register Format ..................................................................................
8-5.
Capture/Compare Control Register 0 Format ...............................................................................
8-6.
16-Bit Timer Output Control Register Format ................................................................................
8-7.
Port Mode Register 3 Format ........................................................................................................
8-8.
External Interrupt Mode Register 0 Format ...................................................................................
8-9.
Sampling Clock Select Register Format ........................................................................................
8-10.
Control Register Settings for Interval Timer Operation ..................................................................
8-11.
Interval Timer Configuration Diagram ............................................................................................
8-12.
Interval Timer Operation Timings ..................................................................................................
8-13.
Control Register Settings for PWM Output Operation ...................................................................
8-14.
Example of D/A Converter Configuration with PWM Output .........................................................
8-15.
TV Tuner Application Circuit Example ...........................................................................................
8-16.
Control Register Settings for PPG Output Operation ....................................................................
8-17.
Control Register Settings for Pulse Width Measurement with Free-Running Counter and
One Capture Register ...................................................................................................................
8-18.
Configuration Diagram for Pulse Width Measurement by Free-Running Counter ........................
8-19.
Timing of Pulse Width Measurement Operation by Free-Running Counter and
One Capture Register (with Both Edges Specified) ......................................................................
8-20.
8-21.
Timing of Pulse Width Measurement Operation with Free-Running Counter
(with Both Edges Specified) ..........................................................................................................
8-22.
Control Register Settings for Pulse Width Measurement with Free-Running Counter and
Two Capture Registers ..................................................................................................................
26
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