Table of Contents
Advertisement
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries)
Figure 17-22. Data Transmission from Master to Slave
(Both Master and Slave Selected 9-Clock Wait) (3 of 3)
Master device operation
SIO0
Data
Write SIO0
COI
ACKD
CMDD
RELD
L
CLD
P27
H
L
WUP
L
BSYE
L
ACKE
CMDT
RELT
CLC
L
WREL
L
SIC
INTCSI0
Transfer line
SCL
1
2 3 4 5 6 7 8
D7
D6
SDA0
Slave device operation
SIO0
Write SIO0
COI
ACKD
CMDD
RELD
CLD
P27
WUP
BSYE
H
ACKE
H
L
CMDT
RELT
L
CLC
L
WREL
H
SIC
INTCSI0
CSIE0
P25
PM25
L
PM27
(c) Stop Condition
9
D5 D4 D3 D2 D1 D0 ACK
FFH
SIO0
SIO0
Address
1 2 3 4
A6 A5 A4 A3
FFH
381
Hide quick links:
Advertisement
Table of Contents
