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(c) Baud rate generator control register (BRGC)
BRGC is set with an 8-bit memory manipulation instruction.
RESET input sets BRGC to 00H.
Symbol
7
6
5
BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
MDL3 MDL2 MDL1 MDL0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
1
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Remark
f
SCK
k
CHAPTER 19 SERIAL INTERFACE CHANNEL 2
4
3
2
1
0
Baud Rate Generator Input Clock Selection
f
/16
0
SCK
f
/17
1
SCK
f
/18
0
SCK
f
/19
1
SCK
f
/20
0
SCK
1
f
/21
SCK
0
f
/22
SCK
1
f
/23
SCK
f
/24
0
SCK
f
/25
1
SCK
f
/26
0
SCK
f
/27
1
SCK
f
/28
0
SCK
f
/29
1
SCK
0
f
/30
SCK
1
f
SCK
: 5-bit counter source clock
: Value set in MDL0 to MDL3 (0
Address
After Reset
R/W
FF73H
00H
R/W
k
14)
k
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
—
469
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