Page 1 User’s Manual µ PD789489 Subseries 8-Bit Single-Chip Microcontrollers µ PD789488 µ PD789489 µ PD78F9488 µ PD78F9489 Document No. U15331EJ4V1UD00 (4th edition) Date Published July 2005 NS CP(K) © Printed in Japan...
Page 2 [MEMO] User’s Manual U15331EJ4V1UD...
Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between V (MIN).
Page 4 EEPROM and FIP are trademarks of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
Page 5 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 6 Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 7 Modification of descriptions in Figure 12-4. Format of Automatic Data Transmit/Receive Interval Specification Register 0 pp.342 to Addition of formal specifications of µ PD789488, 78F9488, 789489, 78F9489) pp.366, 367 Addition of recommended conditions for SOLDERING CONDITIONS Major Revisions in Modified Edition (U15331EJ4V1UD00)
Page 8 µ PD789489 Subseries and design and develop application systems and programs µ µ • PD789489 Subseries: PD789488, 789489, 78F9488, 78F9489 µ PD789489 Subseries: µ PD789489 Subseries User’s Manual assembler and is defined as an sfr variable by the #pragma sfr directive for the C compiler.
Page 9 Conventions Data significance: Active low representation: Note: Caution: Remark: Numerical representation: Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices µ PD789489 Subseries User’s Manual 78K/0S Series Instructions User’s Manual Documents Related to Development Software Tools (User’s Manuals) RA78K0S Assembler Package...
Page 10 Other Related Documents SEMICONDUCTOR SELECTION GUIDE - Products and Packages - Semiconductor Device Mount Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html) Caution The related documents listed above are subject to change without notice.
Page 11: Table Of Contents
CHAPTER 1 GENERAL ... 26 Features ... 26 Applications ... 26 Ordering Information ... 27 Pin Configuration (Top View) ... 28 78K/0S Series Lineup ... 31 Block Diagram... 34 Overview of Functions ... 35 CHAPTER 2 PIN FUNCTIONS... 37 List of Pin Functions ... 37 Description of Pin Functions ...
Page 12 3.1.4 Data memory addressing ... 54 Processor Registers ...58 3.2.1 Control registers... 58 3.2.2 General-purpose registers... 61 3.2.3 Special function registers (SFRs)... 62 Instruction Address Addressing ...66 3.3.1 Relative addressing... 66 3.3.2 Immediate addressing ... 67 3.3.3 Table indirect addressing ... 68 3.3.4 Register addressing ...
Page 13 5.4.5 When subsystem clock is not used ... 104 Subsystem clock ×4 multiplication circuit ... 104 5.4.6 Clock Generator Operation...105 Changing Setting of System Clock and CPU Clock ...106 5.6.1 Time required for switching between system clock and CPU clock... 106 5.6.2 Switching between system clock and CPU clock ...
Page 14 9.4.1 Operation as watchdog timer ... 171 9.4.2 Operation as interval timer ... 172 CHAPTER 10 10-BIT A/D CONVERTER ...173 10.1 10-Bit A/D Converter Functions...173 10.2 10-Bit A/D Converter Configuration ...173 10.3 10-Bit A/D Converter Control Registers ...176 10.4 10-Bit A/D Converter Operation...178 10.4.1 Basic operation of 10-bit A/D converter...
Page 15 14.1 Multiplier Function...267 14.2 Multiplier Configuration ...267 14.3 Multiplier Control Register...269 14.4 Multiplier Operation ...270 CHAPTER 15 REMOTE CONTROLLER RECEIVER ( 15.1 Remote Controller Receiver Functions ...271 15.2 Remote Controller Receiver Configuration...271 15.3 Registers to Control Remote Controller Receiver...277 15.4 Operation of Remote Controller Receiver ...279 15.4.1 Format of type A reception mode ...
Page 16 APPENDIX B NOTES ON TARGET SYSTEM DESIGN ...375 APPENDIX C REGISTER INDEX ...379 Register Index (Register Names in Alphabetic Order)...379 Register Index (Register Symbols Alphabetic Order) ...382 APPENDIX D REVISION HISTORY ...385 µ PD789488, 78F9488, 789489, 78F9489) ...342 User’s Manual U15331EJ4V1UD...
Page 17 Figure No. I/O Circuit Types ...46 µ Memory Map ( PD789488) ...48 µ Memory Map ( PD78F9488)...49 µ Memory Map ( PD789489) ...50 µ Memory Map ( PD78F9489)...51 Data Memory Addressing ( Data Memory Addressing ( Data Memory Addressing ( Data Memory Addressing ( Program Counter Configuration ...58...
Page 18 Figure No. Format of Subclock Control Register...99 Subclock Selection Register Format ...100 External Circuit of Main System Clock Oscillator...101 External Circuit of Subsystem Clock Oscillator...102 Examples of Incorrect Resonator Connection ...103 5-10 Switching Between System Clock and CPU Clock ...107 Block Diagram of 16-Bit Timer 20 ...109 Format of 16-Bit Timer Mode Control Register 20...111 Format of Port Mode Register 3 ...112...
Page 19 Figure No. 7-21 Timing of Square-Wave Output with 16-Bit Resolution ...149 7-22 Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M > N))...151 Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M < N))...152 7-23 7-24 Timing of Carrier Generator Operation (When CR60 = CRH60 = N) ...153...
Page 20 Figure No. 11-4 Format of Asynchronous Serial Interface Mode Register 20 ...191 11-5 Format of Asynchronous Serial Interface Status Register 20 ...193 11-6 Format of Baud Rate Generator Control Register 20 ...194 11-7 Format of Asynchronous Serial Interface Transmit/Receive Data ...204 11-8 Asynchronous Serial Interface Transmission Completion Interrupt Timing ...206 11-9...
Page 21 Figure No. 13-12 Four-Time-Slice LCD Display Pattern and Electrode Connections ...263 13-13 Example of Connecting Four-Time-Slice LCD Panel ...264 13-14 Four-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method) ...265 13-15 Example of Connecting Pins for LCD Driver ...266 14-1 Block Diagram of Multiplier ...268 14-2 Format of Multiplier Control Register 0...269 Multiplier Operation Timing (Example of AAH ×...
Page 22 Figure No. 17-3 Releasing HALT Mode by RESET Input...311 17-4 Releasing STOP Mode by Interrupt...313 17-5 Releasing STOP Mode by RESET Input ...314 18-1 Block Diagram of Reset Function ...315 18-2 Reset Timing by RESET Input ...316 18-3 Reset Timing by Overflow in Watchdog Timer ...316 18-4 Reset Timing by RESET Input in STOP Mode ...316 19-1...
Page 23 Table No. Types of Pin I/O Circuits ...45 Internal ROM Capacity...52 Vector Table...52 Internal High-Speed RAM, Internal Low-Speed RAM Capacity...53 Special Function Registers ...63 Port Functions ...76 Configuration of Port ...76 Port Mode Registers and Output Latch Settings When Using Alternate Functions ...92 Configuration of Clock Generator...95 Maximum Time Required for Switching CPU Clock ...106 16-Bit Timer 20 Configuration ...108...
Page 24 V 15-1 Remote Controller Receiver Configuration ...271 15-2 Noise Elimination Width ...287 µ 16-1 Interrupt Sources ( PD789488, 78F9488) ...291 µ 16-2 Interrupt Sources ( PD789489, 78F9489) ...292 16-3 Flags Corresponding to Interrupt Request Signal Names ...294 16-4 Time from Generation of Maskable Interrupt Request to Servicing ...303 17-1 Operation Statuses in HALT Mode...309...
Page 25: User's Manual U15331Ej4V1Ud
Table No. 21-1 Operand Identifiers and Description Methods ...332 25-1 Surface Mounting Type Soldering Conditions ...366 Distance Between IE System and Conversion Adapter...375 LIST OF TABLES (3/3) Title User’s Manual U15331EJ4V1UD Page...
Page 26: Chapter 1 General
1.1 Features • ROM and RAM capacities Item Part Number µ PD789488 Mask ROM µ PD78F9488 Flash memory µ PD789489 Mask ROM µ PD78F9489 Flash memory • Minimum instruction execution time can be selected from high speed (0.4 µ system clock), low speed (1.6 @32.768 kHz operation with subsystem clock)
Page 27: Ordering Information
1.3 Ordering Information Part Number µ PD789488GC-×××-8BT µ PD789488GK-×××-9EU µ PD78F9488GC-8BT µ PD78F9488GK-9EU µ PD789489GC-×××-8BT µ PD789489GK-×××-9EU µ PD78F9489GC-8BT µ PD78F9489GK-9EU µ PD789488GC-×××-8BT-A µ PD789488GK-×××-9EU-A µ PD78F9488GC-8BT-A µ PD78F9488GK-9EU-A µ PD789489GC-×××-8BT-A µ PD789489GK-×××-9EU-A µ PD78F9489GC-8BT-A µ PD78F9489GK-9EU-A Remarks 1. ××× indicates ROM code suffix. 2.
Page 28: Pin Configuration (Top View)
1.4 Pin Configuration (Top View) µ PD789488, 78F9488 80-pin plastic QFP (14 × 14) µ PD789488GC-×××-8BT µ PD789488GC-×××-8BT-A 80-pin plastic TQFP (fine pitch) (12 × 12) µ PD789488GK-×××-9EU µ PD789488GK-×××-9EU-A 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61...
Page 29 Cautions 1. Connect the IC (Internally Connected) pin directly to V 2. Connect the AV pin to V 3. Connect the AV pin to V Remark The parenthesized values apply to the µ PD789489, 78F9489 80-pin plastic QFP (14 × 14) µ...
Page 30 Notes 1. Whether to use these pins as input port pins (P70 to P73) or segment outputs (S16 to S19) can be selected in 1-bit units by means of a mask option or port function register (refer to 4.3 (3) Port function registers and CHAPTER 20 MASK OPTIONS).
Page 31: 0S Series Lineup
1.5 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Y Subseries products support SMB. Small-scale package, general-purpose applications µ 44-pin PD789046 µ 42-/44-pin PD789026 µ 30-pin PD789088 µ 30-pin PD789074 µ...
Page 32 The major functional differences between the subseries are listed below. Series for General-purpose applications and LCD drive Function Capacity Subseries Name µ Small-scale PD789046 16 KB package, µ PD789026 4 KB to 16 KB general- µ PD789088 16 KB to purpose 32 KB applications...
Page 33 Series for ASSP Function Capacity Subseries Name µ PD789800 8 KB µ Inverter PD789842 8 KB to 16 KB 3 ch control µ On-chip bus PD789852 24 KB to controller 32 KB µ PD789850A 16 KB µ Keyless PD789861 4 KB entry µ...
Page 34: Block Diagram
CPU core memory) RAM space for LCD data Note 4 µ PD789488, 789489 or a port mode register in the µ PD789488 or a port mode register in the User’s Manual U15331EJ4V1UD P00 to P07 Port 0 Port 1 P10 to P11...
Page 35: Overview Of Functions
2. 12 pins are used either as a port function or LCD segment output selected by a mask option or port function register. CHAPTER 1 GENERAL µ µ PD789488 PD78F9488 32 KB 32 KB (flash memory) 1024 bytes −...
Page 36 2. The watchdog timer has watchdog timer and interval timer functions. However, use the watchdog timer by selecting either the watchdog timer function or interval timer function. CHAPTER 1 GENERAL µ µ PD789488 PD78F9488 = 1.8 to 5.5 V = −40 to +85°C • 80-pin plastic QFP (14 × 14) •...
Page 37: Chapter 2 Pin Functions
For mask ROM version, an on-chip pull-up resistor can be specified by mask option. P60 to P67 Input Port 6. 8-bit input port. µ Notes 1. PD789488 and 78F9488 only µ PD789489 and 78F9489 only CHAPTER 2 PIN FUNCTIONS Function User’s Manual U15331EJ4V1UD After Reset Alternate Function...
Page 38 PD789488 and 78F9488 only µ PD789489 and 78F9489 only CHAPTER 2 PIN FUNCTIONS Function µ PD789488, 789489 or a port mode register in µ PD789488, 789489 or a port mode register in Function User’s Manual U15331EJ4V1UD After Reset Alternate Function Input −...
Page 39 Only when segment output is selected by mask option Only when segment output is selected by mask option µ PD789488, 789489 or a port mode register in µ PD789488, 789489 or a port mode register in User’s Manual U15331EJ4V1UD After Reset...
Page 40: Description Of Pin Functions
For the details of the setting, refer to Table 11-2 Serial Interface 20 Operation Mode Setting and 12.3 (1) Serial operation mode register 1A0 (CSIM1A0). CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD µ PD789488, 78F9488),...
Page 41: P30 To P34 (Port 3)
2.2.4 P30 to P34 (Port 3) These pins constitute a 5-bit I/O port. In addition, they also function as timer I/O, external interrupt input, and Note remote control receive data input Port 3 can be specified in the following operation modes in 1-bit units. Port mode In this mode, P30 to P34 function as a 5-bit I/O port.
Page 42: P60 To P67 (Port 6)
µ mask option in the PD789488, 789489 or by a port function register in the 2.2.8 P80 to P87 (Port 8) These pins constitute an 8-bit I/O port. Port 8 can be set in the input or output mode in 1-bit units by port mode register 8 (PM8).
Page 43: Reset
2.2.13 RESET This pin inputs an active-low system reset signal. 2.2.14 X1, X2 These pins are used to connect a crystal resonator for main system clock oscillation. To supply an external clock, input the clock to X1 and input the inverted signal to X2. 2.2.15 XT1, XT2 These pins are used to connect a crystal resonator for subsystem clock oscillation.
Page 44: Ic0 (Mask Rom Version Only)
2.2.21 IC0 (mask ROM version only) The IC0 (Internally Connected) pin is used to set the the normal operation mode, directly connect this pin to the V If there is a potential difference between the IC0 pin and V superimposed on the IC0 pin, the user program may not run correctly. CHAPTER 2 PIN FUNCTIONS µ...
Page 45: Pin I/O Circuits And Recommended Connection Of Unused Pins
CAPH, CAPL – to V µ Notes 1. When PD789488, 78F9488 is used. µ 2. When PD789489, 78F9489 is used. 3. Only when port pin is selected by mask option or port function register. 4. Only when segment output pin is selected by mask option or port function register.
Page 46: I/O Circuit Types
Pin Name I/O Circuit Type – RESET – Type 2 Schmitt-triggered input with hysteresis characteristics. Type 5-A Pull-up enable Data P-ch Output N-ch disable Input enable Type 8-A Pull-up enable Data P-ch Output N-ch disable CHAPTER 2 PIN FUNCTIONS Table 2-1. Types of Pin I/O Circuits (2/2) Recommended Connection of Unused Pins Input Connect to V...
Page 47 Type 13-W Data Output disable Input enable Middle-voltage input buffer Type 17 P-ch P-ch N-ch data P-ch N-ch N-ch CHAPTER 2 PIN FUNCTIONS Figure 2-1. I/O Circuit Types (2/2) Type 13-V Mask Data option Output disable IN/OUT N-ch Input enable Middle-voltage input buffer Type 18 P-ch...
Page 48: Chapter 3 Cpu Architecture
8 0 0 0 H 7 F F F H Program memory space 0 0 0 0 H CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map ( PD789488) Special function registers 8 bits Internal high-speed RAM 1024 8 bits Reserved...
Page 49 Figure 3-2. Memory Map ( PD78F9488) F F F F H Special function registers F F 0 0 H F E F F H Internal high-speed RAM 1024 F B 0 0 H F A F F H F A 1 C H F A 1 B H LCD display RAM Data memory...
Page 50 F F F F H Special function registers F F 0 0 H F E F F H Internal high-speed RAM F B 0 0 H F A F F H F A 1 C H F A 1 B H Data memory F A 0 0 H space...
Page 51 Figure 3-4. Memory Map ( PD78F9489) F F F F H Special function registers F F 0 0 H F E F F H Internal high-speed RAM 1024 F B 0 0 H F A F F H F A 1 C H F A 1 B H LCD display RAM Data memory...
Page 52: Internal Program Memory Space
Vector table area The 46-byte area of addresses 0000H to 002DH is reserved in the PD789488 and 78F9488, and the 48- byte area of address 0000H to 002FH is reserved in the PD789489 and 78F9489 as a vector table area.
Page 53: Internal Data Memory Space
The internal high-speed RAM can also be used as a stack. The internal low-speed RAM cannot be used as a stack. Table 3-3. Internal High-Speed RAM, Internal Low-Speed RAM Capacity Part Number PD789488 PD78F9488 PD789489 PD78F9489 LCD display RAM LCD display RAM is incorporated in the area between FA00H and FA1BH.
Page 54: Data Memory Addressing
Figures 3-5 to 3-8 show the data memory addressing modes. Figure 3-5. Data Memory Addressing ( PD789488) F F F F H...
Page 55 Figure 3-6. Data Memory Addressing ( PD78F9488) F F F F H Special function registers 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H Internal high-speed RAM 1024 8 bits F E 2 0 H...
Page 56 Figure 3-7. Data Memory Addressing ( PD789489) F F F F H Special function registers (SFR) 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H Internal high-speed RAM 1024 8 bits F E 2 0 H...
Page 57 Figure 3-8. Data Memory Addressing ( PD78F9489) F F F F H Special function registers 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H Internal high-speed RAM 1024 8 bits F E 2 0 H...
Page 58: Processor Registers
3.2 Processor Registers The PD789489 Subseries is provided with the following on-chip processor registers. 3.2.1 Control registers The control registers contain special functions to control the program sequence status and stack memory. The program counter, program status word, and stack pointer are control registers. Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed.
Page 59 CHAPTER 3 CPU ARCHITECTURE Interrupt enable flag (IE) This flag controls interrupt request acknowledgement operations of the CPU. When 0, IE is set to the interrupt disabled status (DI), and interrupt requests other than non-maskable interrupts are all disabled. When 1, IE is set to the interrupt enabled status (EI). Interrupt request acknowledgement enable is controlled by the interrupt mask flag for the corresponding interrupt source.
Page 60: Stack Pointer Configuration
Stack pointer (SP) This is a 16-bit register that holds the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-11. Stack Pointer Configuration SP15 SP14 SP13 SP12 SP11 SP10 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory.
Page 61: General-Purpose Registers
3.2.2 General-purpose registers The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL).
Page 62: Special Function Registers (Sfrs)
3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. The special function registers are allocated in the 256-byte area of FF00H to FFFFH. Special function registers can be manipulated, like general-purpose registers, by operation, transfer, and bit manipulation instructions.
Page 63: Special Function Registers
Table 3-4. Special Function Registers (1/3) Address Special Function Register (SFR) Name FF00H Port 0 FF01H Port 1 FF02H Port 2 FF03H Port 3 FF05H Port 5 FF06H Port 6 Note FF07H Port 7 Note FF08H Port 8 FF0AH 8-bit compare register 61 FF0BH 8-bit timer counter 61 FF0CH...
Page 64 Automatic data transmit/receive interval specification register 0 Notes 1. These registers function only in the PD78F9488 and 78F9489; however, writing to these registers in the PD789488 and 789489 will not affect the operation. PD789489 and 78F9489 only CHAPTER 3 CPU ARCHITECTURE...
Page 65 Table 3-4. Special Function Registers (3/3) Address Special Function Register (SFR) Name FF80H A/D converter mode register 0 FF84H Analog input channel specification register 0 FFA0H Serial interface buffer memory 0 FFA1H Serial interface buffer memory 1 FFA2H Serial interface buffer memory 2 FFA3H Serial interface buffer memory 3 FFA4H...
Page 66: Instruction Address Addressing
3.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (for details of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E)).
Page 67: Immediate Addressing
3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space. [Illustration] In case of CALL !addr16 and BR !addr16 instructions CHAPTER 3 CPU ARCHITECTURE...
Page 68: Table Indirect Addressing
3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched.
Page 69: Operand Address Addressing
3.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated with immediate data in an instruction word is directly addressed. [Operand format] Identifier addr16...
Page 70: Short Direct Addressing
3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 71: Special Function Register (Sfr) Addressing
3.4.3 Special function register (SFR) addressing [Function] The memory-mapped special function registers (SFRs) are addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can also be accessed with short direct addressing.
Page 72: Register Addressing
3.4.4 Register addressing [Function] In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose register to be accessed is specified by a register specification code or functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
Page 73: Register Indirect Addressing
3.4.5 Register indirect addressing [Function] In the register indirect addressing mode, memory is manipulated according to the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register pair specification code in an instruction code.
Page 74: Based Addressing
3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits.
Page 75: Chapter 4 Port Functions
4.1 Port Functions µ PD789489 Subseries provides the ports shown in Figure 4-1, enabling various methods of control. The functions of each port are shown in Table 4-1. Numerous other functions are provided that can be used in addition to the digital I/O port functions. For more information on these additional functions, see CHAPTER 2 PIN FUNCTIONS.
Page 76: Port Configuration
• Flash memory version Total: 21 (software control only) CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions Function µ PD789488, 789489 or a port mode register in µ PD789488, 789489 or a port mode register in Table 4-2. Configuration of Port Configuration µ...
Page 77: Port 0
Pull-up resistor option register B0 Port mode register Port 0 read signal Port 0 write signal µ Notes 1. When PD789488, 78F9488 is used µ 2. When PD789489, 78F9489 is used CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P00 to P07 User’s Manual U15331EJ4V1UD...
Page 78: Port 1
4.2.2 Port 1 This is a 2-bit I/O port with an output latch. Port 1 can be specified in the input or output mode in 1-bit units by using port mode register 1 (PM1). When using the P10 and P11 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register B1 (PUB1).
Page 79: Port 2
4.2.3 Port 2 This is a 6-bit I/O port with an output latch. Port 2 can be specified in the input or output mode in 1-bit units by using port mode register 2 (PM2). When using the P20 to P25 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register B2 (PUB2).
Page 80: Block Diagram Of P21
PUB2 PUB21 PORT Output latch (P21) PM21 Alternate function PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P21 User’s Manual U15331EJ4V1UD P-ch P21/SO20/TxD20...
Page 81: Block Diagram Of P22 And P25
CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P22 and P25 PUB2 PUB22, PUB25 Alternate function PORT Output latch (P22, P25) PM22, PM25 PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U15331EJ4V1UD P-ch P22/SI20/...
Page 82: Block Diagram Of P23
PUB2 PUB23 Alternate function PORT Output latch (P23) PM23 Alternate function PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P23 User’s Manual U15331EJ4V1UD P-ch P23/SCK10...
Page 83: Block Diagram Of P24
CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P24 PUB2 PUB24 PORT Output latch (P24) PM24 Alternate function PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U15331EJ4V1UD P-ch P24/SO10...
Page 84: Port 3
4.2.4 Port 3 This is a 5-bit I/O port with an output latch. Port 3 can be specified in the input or output mode in 1-bit units by using port mode register 3 (PM3). When using the P30 to P34 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register B3 (PUB3).
Page 85: Block Diagram Of P34
Alternate function PORT Output latch (P34) PM34 PUB3: Pull-up resistor option register B3 Port mode register Port 3 read signal Port 3 write signal User’s Manual U15331EJ4V1UD µ PD789488, 78F9488 is used µ PD789489, 78F9489 is used P-ch P-ch P34/RIN...
Page 86: Port 5
4.2.5 Port 5 This is a 4-bit N-ch open-drain I/O port with an output latch. Port 5 can be specified in the input or output mode in 1-bit units by using port mode register 5 (PM5). For a mask ROM version, use of an on-chip pull-up resistor can be specified by a mask option.
Page 87: Port 6
This port is also used for the analog input of an A/D converter and key return signal input Figure 4-12 shows a block diagram of port 6. µ Note PD789489 and 78F9489 only. Figure 4-12. Block Diagram of P60 to P67 (1/2) µ (a) When PD789488,78F9488 is used P60/ANI0 to P67/ANI7 A/D converter − User’s Manual U15331EJ4V1UD...
Page 88 Figure 4-12. Block Diagram of P60 to P67 (2/2) KRM01 KRM010, KRM014 to KRM017 A/D converter KRM01: Key return mode register 01 Port 6 read signal CHAPTER 4 PORT FUNCTIONS µ (b) When PD789489, 78F9489 is used Alternate function − User’s Manual U15331EJ4V1UD P60/ANI0/KR10 to P67/ANI7/KR17...
Page 89: Port 7
This is a 4-bit input-only port. Only the bits for which the port function is selected can be used, by using a mask µ option in the PD789488 and 789489 or port function register 7 (PF7) in the Figure 4-13 shows a block diagram of port 7. Figure 4-13. Block Diagram of P70 to P73...
Page 90: Port 8
µ using a mask option in the PD789488 and 789489 or port function register 8 (PF8) in the Port 8 can be specified in the input or output mode in 1-bit units by using port mode register 8 (PM8). RESET input sets this port to input mode.
Page 91: Registers Controlling Port Function
4.3 Registers Controlling Port Function The ports are controlled by the following three types of registers. • Port mode registers (PM0 to PM3, PM5, PM8) • Pull-up resistor option registers (PUB0 to PUB3) • Port function registers (PF7, PF8) ( Port mode registers (PM0 to PM3, PM5, PM8) Input and output can be specified in 1-bit units.
Page 92: Port Mode Registers And Output Latch Settings When Using Alternate Functions
Table 4-3. Port Mode Registers and Output Latch Settings When Using Alternate Functions Pin Name P00 to P07 KR0 to KR7 or KR00 to KR07 INTP0 TO50 TMI60 INTP1 TO60 INTP2 TMI61 TO61 INTP3 CPT20 TO20 µ RIN ( PD789489, 78F9489 only) Remark ×: don’t care PM××: Port mode register...
Page 93: Format Of Pull-Up Resistor Option Registers
PF7 and PF8 are set via a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to 00H. Caution This register is valid only in the µ PD789488 and 789489 will simply make it invalid, causing no operational effect. Figure 4-17. Port Function Register Format Symbol <7>...
Page 94: Port Function Operation
4.4 Port Function Operation The operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 Writing to I/O port In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port.
Page 95: Chapter 5 Clock Generator
5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are used. • Main system clock oscillator This circuit oscillates at 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC).
Page 96 Subsystem clock oscillator Subsystem clock oscillator STOP MCC PCC1 Processor clock control register (PCC) Remark or 8f CHAPTER 5 CLOCK GENERATOR µ PD789488, 789489) ×4 ×2 multiplication multiplication circuit circuit Mask option Prescaler CSS0 Subclock control register (CSS) Internal bus User’s Manual U15331EJ4V1UD...
Page 97 Figure 5-2. Clock Generator Block Diagram ( Internal bus Subclock oscillation mode register (SCKM) FRC SCC Subsystem clock oscillator Main system clock oscillator STOP MCC PCC1 Processor clock control register (PCC) Remark or 8f CHAPTER 5 CLOCK GENERATOR µ PD78F9488, 78F9489) ×...
Page 98: Registers Controlling Clock Generator
5.3 Registers Controlling Clock Generator The clock generator is controlled by the following four registers. • Processor clock control register (PCC) • Subclock oscillation mode register (SCKM) • Subclock control register (CSS) • Subclock selection register (SSCK) ( Processor clock control register (PCC) This register is used to select the CPU clock and set the frequency division ratio.
Page 99: Format Of Subclock Oscillation Mode Register
Subclock oscillation mode register (SCKM) SCKM selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock. SCKM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SCKM to 00H. Figure 5-4. Format of Subclock Oscillation Mode Register Symbol SCKM On-chip feedback resistor used...
Page 100: Subclock Selection Register Format
SSCK is set via a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Caution This register is valid only in the µ PD789488 and 789489 will simply make it invalid, causing no operational effect. Figure 5-6. Subclock Selection Register Format Symbol SSCK Operation stopped (subsystem clock source (32.768 kHz) supplied to the CPU)
Page 101: System Clock Oscillators
5.4 System Clock Oscillators 5.4.1 Main system clock oscillator The main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the inverted signal to the X2 pin.
Page 102: Subsystem Clock Oscillator
5.4.2 Subsystem clock oscillator The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz TYP.) connected across the XT1 and XT2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the XT1 pin, and input the inverted signal to the XT2 pin.
Page 103: Example Of Incorrect Resonator Connection
5.4.3 Example of incorrect resonator connection Figure 5-9 shows examples of incorrect resonator connection. Figure 5-9. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (c) Wiring near high fluctuating current Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to XT2 in series.
Page 104: Divider Circuit
Figure 5-9. Examples of Incorrect Resonator Connection (2/2) Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to XT2 in series. 5.4.4 Divider circuit The divider circuit divides the output of the main system clock oscillator (f 5.4.5 When subsystem clock is not used If the subsystem clock is not necessary, for example, for low-power consumption operation or clock operation, handle the XT1 and XT2 pins as follows.
Page 105: Clock Generator Operation
5.0 MHz operation) of the main system clock is selected when the µ s and 1.6 µ PD789488 and 789489 or the subclock selection register µ s: a circuit to multiply the subsystem clock by 4 is User’s Manual U15331EJ4V1UD µ...
Page 106: Changing Setting Of System Clock And Cpu Clock
5.6 Changing Setting of System Clock and CPU Clock 5.6.1 Time required for switching between system clock and CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock control register (CSS).
Page 107: Switching Between System Clock And Cpu Clock
5.6.2 Switching between system clock and CPU clock The following figure illustrates how the CPU clock and system clock switch. Figure 5-10. Switching Between System Clock and CPU Clock RESET Interrupt request signal System clock CPU clock <1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released when the RESET pin is later made high, and the main system clock starts oscillating.
Page 108: Chapter 6 16-Bit Timer 20
6.1 16-Bit Timer 20 Functions 16-bit timer 20 has the following functions. • Timer interrupt • Timer output • Count value capture Timer interrupt An interrupt is generated when a count value and compare value match. Timer output Timer output can be controlled when a count value and compare value match. Count value capture The count value of 16-bit timer counter 20 (TM20) is latched into a capture register in synchronization with the capture trigger and retained.
Page 109: Block Diagram Of 16-Bit Timer 20
Figure 6-1. Block Diagram of 16-Bit Timer 20 16-bit timer mode control register 20 (TMC20) TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 16-bit compare register 20 (CR20) 16-bit timer counter 20 (TM20) Timer 61 interrupt request signal CPT20/TO20 16-bit capture Edge detector /INTP3/P33 register 20 (TCP20)
Page 110: Registers Controlling 16-Bit Timer 20
16-bit counter read buffer 20 This buffer is used to latch and hold the count value for TM20. 6.3 Registers Controlling 16-Bit Timer 20 16-bit timer 20 is controlled by the following three registers. • 16-bit timer mode control register 20 (TMC20) •...
Page 111: Format Of 16-Bit Timer Mode Control Register 20
Figure 6-2. Format of 16-Bit Timer Mode Control Register 20 Symbol <7> <6> TMC20 TOD20 TOF20 CPT201 TOD20 Timer output is “0” Timer output is “1” TOF20 Reset and clear by software Set by overflow of 16-bit timer CPT201 CPT200 Capture operation disabled Rising edge of CPT20 pin Falling edge of CPT20 pin...
Page 112: Format Of Port Mode Register 3
(2) Port mode register 3 (PM3) This register is used to set the I/O mode of port 3 in 1-bit units. When using the P33/INTP3/CPT20/TO20 pin as a capture input (CPT20), set PM33 to 1. When using the above pin as a timer output (TO20), set the PM33 and P33 output latches to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
Page 113: 16-Bit Timer 20 Operation
6.4 16-Bit Timer 20 Operation 6.4.1 Operation as timer interrupt 16-bit timer 20 can generate interrupts repeatedly each time the free-running counter value reaches the value set to CR20. Since this counter is not cleared and holds the count even after an interrupt is generated, the interval time is equal to one cycle of the count clock set in TCL201 and TCL200.
Page 114: Timing Of Timer Interrupt Operation
Figure 6-5. Timing of Timer Interrupt Operation Count clock TM20 count value 0000H 0001H CR20 INTTM20 TO20 TOF20 Remark N = 0000H to FFFFH CHAPTER 6 16-BIT TIMER 20 FFFFH 0000H 0001H Interrupt acknowledgement Overflow flag set User’s Manual U15331EJ4V1UD Interrupt acknowledgement...
Page 115: Operation As Timer Output
6.4.2 Operation as timer output 16-bit timer 20 can invert the timer output repeatedly each time the free-running counter value reaches the value set to CR20. Since this counter is not cleared and holds the count even after the timer output is inverted, the interval time is equal to one cycle of the count clock set in TCL201 and TCL200.
Page 116: Capture Operation
6.4.3 Capture operation The capture operation consists of latching the count value of 16-bit timer counter 20 (TM20) into a capture register in synchronization with a capture trigger, and retaining the count value. Set TMC20 as shown in Figure 6-8 to allow the 16-bit timer to start the capture operation. Figure 6-8.
Page 117: 16-Bit Timer Counter 20 Readout
6.4.4 16-bit timer counter 20 readout The count value of 16-bit timer counter 20 (TM20) is read out using a 16-bit manipulation instruction. TM20 readout is performed via the counter read buffer. The counter read buffer latches the TM20 count value, the buffer operation is held pending at the CPU clock falling edge after the read signal of the TM20 lower byte rises, and the count value is retained.
Page 118: Cautions On Using 16-Bit Timer 20
6.5 Cautions on Using 16-Bit Timer 20 6.5.1 Restrictions when rewriting 16-bit compare register 20 (1) Disable interrupts (TMMK20 = 1) and inversion control of timer output (TOC20 = 0) before rewriting the compare register (CR20). If the value in CR20 is rewritten in the interrupt-enabled state, an interrupt request may occur at the moment of rewrite.
Page 119 <Countermeasure B> When rewriting using 16-bit access <1> Disable interrupts (TMMK20 = 1) and inversion control of timer output (TOC20 = 0). <2> Rewrite CR20 (16 bits). <3> Wait for one cycle or more of the count clock. <4> Clear the interrupt request flag (TMIF20). <5>...
Page 120: Chapter 7 8-Bit Timers 50, 60, And 61
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.1 Functions of 8-Bit Timers 50, 60, and 61 One 8-bit timer channel (timer 50) and two 8-bit timer/event counter channels (timer 60 and 61) are incorporated in µ PD789489 Subseries. The operation modes listed in the following table can be set via mode register settings. Mode 8-bit timer counter mode (stand-alone mode)
Page 121: Block Diagram Of 24-Bit Event Counter
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 (5) PPG output mode (PPG: Programmable Pulse Generator) Pulses are output using any cycle or duty ratio (pulse width) set (both the cycle and pulse width are programmable). (6) 24-bit event counter mode Operation as an external event counter with 24-bit resolution is enabled using 16-bit timer 20 and timer 61.
Page 122: Configuration Of 8-Bit Timers 50, 60, And 61
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.2 Configuration of 8-Bit Timers 50, 60, and 61 8-bit timers 50, 60, and 61 include the following hardware. Table 7-2. Configuration of 8-Bit Timers 50, 60, and 61 Item 8 bits × 3 (TM50, TM60, TM61) Timer counter Compare registers: 8 bits ×...
Page 123: Block Diagram Of Timer 50
8-bit timer mode control register 50 (TMC50) TCE50 TEG50 TCL502 TCL501 TCL500 Bit 7 of TM60 (from Figure 7-3(A)) Timer 60 interrupt request signal (from Figure 7-3(B)) Carrier clock (from Figure 7-3(C)) Cascade connection mode Figure 7-2. Block Diagram of Timer 50 Internal bus TMD501 TMD500...
Page 124: Block Diagram Of Timer 60
8-bit timer mode control register 60 (TMC60) TCE60 TCL602 TCL601 TCL600 TMD601 TMD600 TOE600 Decoder TMI60/TO50/ INTP0/P30 PPG mode Cascade connection mode To Figure 7-2(D) Count operation start signal to timer 50 (in cascade connection mode) Figure 7-3. Block Diagram of Timer 60 Internal bus Carrier generator output control register 60 (TCA60)
Page 125: Block Diagram Of Timer 61
8-bit timer mode control register 61 (TMC61) TCE61 TCL612 TCL611 TCL610 TMD611 TMD610 TOE610 Decoder TMI61/TO61 /INTP2/P32 Figure 7-4. Block Diagram of Timer 61 Internal bus 8-bit H width compare 8-bit compare register 61 (CRH61) register 61 (CR61) Selector Match 8-bit timer counter 61 (TM61) Clear...
Page 126: Block Diagram Of Output Controller (Timer 60)
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-5. Block Diagram of Output Controller (Timer 60) TOE60 RMC60 Carrier generator mode (1) 8-bit compare register 50 (CR50) This 8-bit register is used to continually compare the value set to CR50 with the count value in 8-bit timer counter 50 (TM50) and to issue an interrupt request (INTTM50) when a match occurs.
Page 127 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 (4) 8-bit H width compare registers 60 and 61 (CRH60, CRH61) In carrier generator mode and PPG output mode, the high-level width of timer output is set by writing a value to CRH6n. This 8-bit register is used to continually compare the value set to CRH6n with the count value in 8-bit timer counter 6n (TM6n) and to issue an interrupt request (INTTM6n) when a match occurs.
Page 128: Control Registers For 8-Bit Timers 50, 60, And 61
7.3 Control Registers for 8-Bit Timers 50, 60, and 61 8-bit timers 50, 60, and 61 are controlled by the following six registers. • 8-bit timer mode control register 50 (TMC50) • 8-bit timer mode control register 60 (TMC60) • Carrier generator output control register 60 (TCA60) •...
Page 129 Figure 7-6. Format of 8-Bit Timer Mode Control Register 50 (2/2) Symbol <7> <6> TMC50 TCE50 TEG50 TCL502 TOE50 Output disabled Output enabled Notes 1. Since the count operation is controlled by TCE60 (bit 7 of TMC60) in cascade connection mode, any setting for TCE50 is ignored.
Page 130: Format Of 8-Bit Timer Mode Control Register 60
Figure 7-7. Format of 8-Bit Timer Mode Control Register 60 Symbol <7> TMC60 TCE60 TCL602 TCE60 Clear TM60 count value and stop operation (the count value is also cleared for TM50 in cascade connection mode) Start count operation (the count operation is also started for TM50 in cascade connection mode) TCL602 TCL601 TCL600...
Page 131: Format Of Carrier Generator Output Control Register 60
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 (3) Carrier generator output control register 60 (TCA60) This register is used to set the timer output data in carrier generator mode. TCA60 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.
Page 132: Format Of 8-Bit Timer Mode Control Register 61
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 (4) 8-bit timer mode control register 61 (TMC61) 8-bit timer mode control register 61 (TMC61) is used to control the timer 61 count clock setting and the operation mode setting. TMC61 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.
Page 133: Format Of Port Mode Register 3
(5) Port mode register 3 (PM3) This register is used to set the I/O mode of port 3 in 1-bit units. When using the P30/INTP0/TO50/TMI60 pin as a timer output (TO50), set PM30 and the P30 output latch to 0. When used as a timer input (TMI60), set PM30 to 1.
Page 134: Operation Of 8-Bit Timers 50, 60, And 61
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.4 Operation of 8-Bit Timers 50, 60, and 61 7.4.1 Operation as 8-bit timer counter Timer 50, timer 60, and timer 61 can be independently used as 8-bit timer counters. The following modes can be used for the 8-bit timer counter. •...
Page 135: Interval Time Of Timer 50
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 TCL502 TCL501 TCL500 Minimum Interval Time µ (0.2 µ (1.6 (25.6 (30.5 Input cycle of timer 60 match signal Input cycle of timer 60 output Remarks 1. f Main system clock oscillation frequency 2.
Page 136: Timing Of Interval Timer Operation With 8-Bit Resolution (When Crnm Is Set To 00H)
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-11. Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation) Count clock TMnm CRnm TCEnm Count start INTTMnm TOnm Remarks 1. Interval time = (N + 1) × t: N = 00H to FFH 2.
Page 137: Timing Of Interval Timer Operation With 8-Bit Resolution (When Crnm Is Set To Ffh)
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-13. Timing of Interval Timer Operation with 8-Bit Resolution (When CRnm Is Set to FFH) Count clock TMnm CRnm TCEnm Count start INTTMnm TOnm Remark nm = 50, 60, 61 Figure 7-14. Timing of Interval Timer Operation with 8-Bit Resolution (When CRnm Changes from N to M (N <...
Page 138 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-15. Timing of Interval Timer Operation with 8-Bit Resolution (When CRnm Changes from N to M (N > M)) Count clock N − 1 TMnm Clear CRnm TCEnm INTTMnm TOnm 00H ≤ M < N ≤ FFH Remark nm = 50, 60, 61 Clear...
Page 139: Timing Of Interval Timer Operation With 8-Bit Resolution (When Timer 60 Match Signal Is Selected For Timer 50 Count Clock)
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-16. Timing of Interval Timer Operation with 8-Bit Resolution (When Timer 60 Match Signal Is Selected for Timer 50 Count Clock) Timer 60 count clock TM60 CR60 TCE60 Count start INTTM60 Input clock to timer 50 (timer 60 match signal) TM50...
Page 140: Timing Of Operation Of External Event Counter With 8-Bit Resolution
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Operation as external event counter with 8-bit resolution (timer 60 and timer 61 only) The external event counter counts the number of external clock pulses input to the TMI6m pin by using 8-bit timer counter 6m (TM6m).
Page 141: Square-Wave Output Range Of Timer 50
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Operation as square-wave output with 8-bit resolution Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare register nm (CRnm). To operate timer nm for square-wave output, settings must be made in the following sequence. <1>...
Page 142: Timing Of Square-Wave Output With 8-Bit Resolution
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Table 7-7. Square-Wave Output Range of Timer 60 TCL602 TCL601 TCL600 Minimum Pulse Width (0.2 (0.8 input cycle /2 input cycle input cycle input cycle Remarks 1. f Main system clock oscillation frequency 2.
Page 143: Operation As 16-Bit Timer Counter
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.4.2 Operation as 16-bit timer counter Timer 50 and timer 60 can be used as a 16-bit timer counter using cascade connection. In this case, 8-bit timer counter 50 (TM50) is the higher 8 bits and 8-bit timer counter 60 (TM60) is the lower 8 bits. 8-bit timer 60 controls reset and clear.
Page 144: Interval Time With 16-Bit Resolution
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Table 7-9. Interval Time with 16-Bit Resolution TCL602 TCL601 TCL600 Minimum Interval Time (0.2 (0.8 input cycle /2 input cycle input cycle input cycle Remarks 1. f Main system clock oscillation frequency 2.
Page 145: Timing Of Interval Timer Operation With 16-Bit Resolution
Count clock TM60 count value Not cleared because TM50 does not match CR60 TCE60 Count start TM50 count pulse TM50 CR50 INTTM60 Interrupt not generated because TM50 does not match TO60 Interval time = (256X + N + 1) × t: X = 00H to FFH, N = 00H to FFH Remark Figure 7-19.
Page 146 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Operation as external event counter with 16-bit resolution The external event counter counts the number of external clock pulses input to the TMI60 pin by TM50 and TM60. To operate as an external event counter with 16-bit resolution, settings must be made in the following sequence.
Page 147: Timing Of External Event Counter Operation With 16-Bit Resolution
Figure 7-20. Timing of External Event Counter Operation with 16-Bit Resolution TMI60 pin input TM60 count value Not cleared because TM50 does not match CR60 TCE60 Count start TM50 count pulse TM50 CR50 INTTM60 Interrupt not generated because TM50 does not match Remark X = 00H to FFH, N = 00H to FFH FFH 00H...
Page 148: Square-Wave Output Range With 16-Bit Resolution
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Operation as square-wave output with 16-bit resolution Square waves of any frequency can be output at an interval specified by the count value preset in CR50 and CR60. To operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence. <1>...
Page 149: Timing Of Square-Wave Output With 16-Bit Resolution
Count clock TM60 count value Not cleared because TM50 does not match CR60 TCE60 Count start TM50 count pulse TM50 CR50 INTTM60 Interrupt not generated because TM50 does not match TO60 Note Note The initial value of TO60 is low level when output is enabled. Remark X = 00H to FFH, N = 00H to FFH Figure 7-21.
Page 150: Operation As Carrier Generator
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.4.3 Operation as carrier generator An arbitrary carrier clock generated by TM60 can be output in the cycle set in TM50. To operate timer 50 and timer 60 as carrier generators, settings must be made in the following sequence. <1>...
Page 151: Timing Of Carrier Generator Operation (When Cr60 = N, Crh60 = M (M > N))
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-22. Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M > N)) TM60 count clock TM60 count value CR60 CRH60 TCE60 Count start INTTM60 Carrier clock TM50 count clock TM50 count value...
Page 152: Timing Of Carrier Generator Operation (When Cr60 = N, Crh60 = M (M < N))
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-23. Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M < N)) TM60 count clock TM60 count value CR60 CRH60 TCE60 Count start INTTM60 Carrier clock TM50 count clock TM50 count value...
Page 153: Timing Of Carrier Generator Operation (When Cr60 = Crh60 = N)
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-24. Timing of Carrier Generator Operation (When CR60 = CRH60 = N) TM60 count clock TM60 count value Clear CR60 CRH60 TCE60 Count start INTTM60 Carrier clock TM50 count clock TM50 count value CR50 TCE50...
Page 154: Pwm Output Mode Operation (Timer 50)
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.4.4 PWM output mode operation (timer 50) In the PWM output mode, TO50 becomes high level when TM50 overflows, and TO50 becomes low level when CR50 and TM50 match. It is thus possible to output a pulse with any duty ratio (free-running). To operate timer 50 in the PWM output mode, settings must be made in the following sequence.
Page 155: Operation Timing When Overwriting Cr50 (When Rising Edge Is Selected)
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-26. Operation Timing When Overwriting CR50 (When Rising Edge Is Selected) When setting CR50 > TM50 after overflow Count clock TM50 Overflow CR50 TCE50 Count start INTTM50 TO50 When setting CR50 < TM50 after overflow Count clock TM50 Overflow...
Page 156: Operation Timing In Pwm Output Mode (When Both Edges Are Selected)
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-27. Operation Timing in PWM Output Mode (When Both Edges Are Selected) CR50 = Even number Count clock TM50 Overflow CR50 TCE50 Count start INTTM50 TO50 When CR50 = Odd number Count clock TM50 2N + 1...
Page 157 CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-28. Operation Timing in PWM Output Mode (When Both Edges Are Selected) (When CR50 Is Overwritten) Count clock TM50 Overflow CR50 TCE50 Count start INTTM50 TO50 Remark N = 00H to FFH Overflow CR50 overwrite User’s Manual U15331EJ4V1UD...
Page 158: Ppg Output Mode Operation (Timer 60 And Timer 61)
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.4.5 PPG output mode operation (timer 60 and timer 61) In the PPG output mode, a pulse of any duty ratio can be output by setting a low-level width using CR6m and a high-level width using CRH6m.
Page 159: Ppg Output Mode Timing (When Cr6M And Crh6M Are Overwritten)
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 Figure 7-29. PPG Output Mode Timing (Basic Operation) Count clock TM6m count value Clear CR6m CRH6m TCE6m Count start INTTM6m Note TO6m Note The initial value of TO6m is low level when output is enabled (TOE6m0 = 1). Remark N, M = 00H to FFH m = 0, 1...
Page 160: Cautions On Using 8-Bit Timers 50, 60, And 61
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.5 Cautions on Using 8-Bit Timers 50, 60, and 61 Error on starting timer An error of up to 1.5 clocks is included in the time between the timer being started and a match signal being generated.
Page 161: Chapter 8 Watch Timer
8.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch and interval timers can be used at the same time. Figure 8-1 shows a block diagram of the watch timer. Watch timer interrupt time selection register (WTIM) CHAPTER 8 WATCH TIMER...
Page 162: Configuration Of Watch Timer
(1) Watch timer An interrupt request (INTWT) occurs at an interval of 0.5 second when using either the 4.19 MHz main system clock or the 32.768 kHz subsystem clock. Also, an interrupt request (INTWT) occurs at an interval of 1.0 seconds when using the 32.768 kHz subsystem clock via a setting in the watch timer interrupt time selection register (WTIM).
Page 163: Control Registers For Watch Timer
8.3 Control Registers for Watch Timer The watch timer is controlled by the following registers. • Watch timer mode control register (WTM) • Watch timer interrupt time selection register (WTIM) (1) Watch timer mode control register (WTM) This register is used to control the watch timer count clock, operation enable/disable status, prescaler interval time, and the 5-bit counter operation.
Page 164: Format Of Watch Timer Interrupt Time Selection Register
(2) Watch timer interrupt time selection register (WTIM) This register is used to set the interrupt time by selecting either the source clock or the clock divided by 2 for the subsystem clock to be input to watch timer. WTIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.
Page 165: Watch Timer Operation
8.4 Watch Timer Operation 8.4.1 Operation as watch timer The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used to enable the watch timer to operate at 0.5-second intervals. Also, an interrupt request (INTWT) occurs at an interval of 1.0 seconds when using the 32.768 kHz subsystem clock via a setting in the watch timer interrupt time selection register (WTIM).
Page 166: Watch Timer/Interval Timer Operation Timing
Figure 8-4. Watch Timer/Interval Timer Operation Timing 5-bit counter Start Count clock Watch timer interrupt INTWT Watch timer interrupt time (0.5 s) Interval timer interrupt INTWTI Caution When operation of the watch timer and 5-bit counter operation is enabled by setting bit 0 (WTM0) of the watch timer mode control register (WTM) to 1, the interval until the first interrupt request (INTWT) is generated after the register is set does not exactly match the watch timer interrupt time (0.5 s).
Page 167: Chapter 9 Watchdog Timer
9.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). Watchdog timer The watchdog timer is used to detect a program loop. When a program loop is detected, a non-maskable interrupt or the RESET signal can be generated.
Page 168: Watchdog Timer Configuration
9.2 Watchdog Timer Configuration The watchdog timer includes the following hardware. Table 9-3. Configuration of Watchdog Timer Item Control registers Watchdog timer clock selection register (WDCS) Watchdog timer mode register (WDTM) Figure 9-1. Block Diagram of Watchdog Timer Prescaler WDCS2 WDCS1 WDCS0 Watchdog timer clock selection register (WDCS) CHAPTER 9 WATCHDOG TIMER...
Page 169: Watchdog Timer Control Registers
9.3 Watchdog Timer Control Registers The watchdog timer is controlled by the following two registers. • Watchdog timer clock selection register (WDCS) • Watchdog timer mode register (WDTM) Watchdog timer clock selection register (WDCS) This register sets the watchdog timer count clock. WDCS is set with an 8-bit memory manipulation instruction.
Page 170: Format Of Watchdog Timer Mode Register
Watchdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 9-3. Format of Watchdog Timer Mode Register Symbol <7>...
Page 171: Watchdog Timer Operation
9.4 Watchdog Timer Operation 9.4.1 Operation as watchdog timer The watchdog timer detects a program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (program loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (WDCS0 to WDCS2) of watchdog timer clock selection register (WDCS).
Page 172: Operation As Interval Timer
9.4.2 Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at intervals specified by a preset count value.
Page 173: Chapter 10 10-Bit A/D Converter
CHAPTER 10 10-BIT A/D CONVERTER 10.1 10-Bit A/D Converter Functions The 10-bit A/D converter is a 10-bit resolution converter used to convert analog inputs into digital signals. This converter can control eight channels (ANI0 to ANI7) of analog inputs. A/D conversion can only be started by software. One of analog inputs ANI0 to ANI7 is selected for A/D conversion.
Page 174: Block Diagram Of 10-Bit A/D Converter
Figure 10-1. Block Diagram of 10-Bit A/D Converter ANI0/P60 ANI1/P61 ANI2/P62 ANI3/P63 ANI4/P64 ANI5/P65 ANI6/P66 ANI7/P67 ADS02 ADS01 ADS00 Analog input channel specification register 0 (ADS0) Successive approximation register (SAR) The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (MSB).
Page 175 CHAPTER 10 10-BIT A/D CONVERTER Sample & hold circuit The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. The sampled analog input voltage is held during A/D conversion. Voltage comparator The voltage comparator compares an analog input with the voltage output by the series resistor string.
Page 176: 10-Bit A/D Converter Control Registers
10.3 10-Bit A/D Converter Control Registers The 10-bit A/D converter is controlled by the following two registers. • A/D converter mode register 0 (ADML0) • Analog input channel specification register 0 (ADS0) A/D converter mode register 0 (ADML0) ADML0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion. ADML0 is set with a 1-bit or 8-bit memory manipulation instruction.
Page 177: Format Of Analog Input Channel Specification Register 0
Cautions 1. Start conversion (ADCS0 = 1) after 14 If ADCE0 is not used, the conversion result immediately after the setting of bit 7 (ADCS0) is undefined. 2. The conversion result may be undefined after ADCS0 has been cleared to 0. To read the conversion result, perform the read operation during A/D conversion.
Page 178: 10-Bit A/D Converter Operation
10.4 10-Bit A/D Converter Operation 10.4.1 Basic operation of 10-bit A/D converter <1> Bit 0 of A/D converter mode register 0 (ADML0) is set (ADCE0 = 1). <2> Select a channel for A/D conversion, using analog input channel specification register 0 (ADS0). µ...
Page 179: Input Voltage And Conversion Result
Figure 10-4. Basic Operation of 10-Bit A/D Converter Sampling time A/D converter Sampling operation Undefined ADCRL0 INTAD0 A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADML0) is reset (0) by software. If an attempt is made to write to ADML0 or analog input channel specification register 0 (ADS0) during A/D conversion, the A/D conversion in progress is canceled.
Page 180: Relationship Between Analog Input Voltage And A/D Conversion Result
Figure 10-5. Relationship Between Analog Input Voltage and A/D Conversion Result 1,023 1,022 1,021 A/D conversion result (ADCRL0) CHAPTER 10 10-BIT A/D CONVERTER 2,043 1,022 2,048 1,024 2,048 1,024 2,048 1,024 2,048 1,024 Input voltage/AV User’s Manual U15331EJ4V1UD 2,045 1,023 2,047 2,048 1,024...
Page 181: Operation Mode Of 10-Bit A/D Converter
10.4.3 Operation mode of 10-bit A/D converter The A/D converter is initially in select mode. In this mode, analog input channel specification register 0 (ADS0) is used to select an analog input channel from ANI0 to ANI7 for A/D conversion. A/D conversion can be started only by software, that is, by setting A/D converter mode register 0 (ADML0).
Page 182: Cautions Related To 10-Bit A/D Converter
10.5 Cautions Related to 10-Bit A/D Converter Current consumption in standby mode In standby mode, the A/D converter stops operation. Clearing bit 7 (ADCS0) and bit 0 (ADCE0) of A/D converter mode register 0 (ADML0) to 0 can reduce the current consumption. Figure 10-7 shows how to reduce the current consumption in standby mode.
Page 183: Conversion Result Read Timing (If Conversion Result Is Normal)
CHAPTER 10 10-BIT A/D CONVERTER Timing of undefined A/D conversion result The A/D conversion value may become undefined if the timing of the completion of A/D conversion and the timing to stop the A/D conversion operation conflict. Therefore, read the A/D conversion result while the A/D conversion operation is in progress.
Page 184: Analog Input Pin Handling
Noise prevention To maintain a resolution of 10 bits, watch for noise at the AV impedance of the analog input source, the larger the effect by noise. To reduce noise, attach an external capacitor to the relevant pins as shown in Figure 10-10. C = 100 to 1,000 pF ANI0 to ANI7 The analog input pins (ANI0 to ANI7) are alternate-function pins.
Page 185: A/D Conversion End Interrupt Request Generation Timing
CHAPTER 10 10-BIT A/D CONVERTER Interrupt request flag (ADIF0) Changing the contents of A/D converter mode register 0 (ADML0) does not clear the interrupt request flag (ADIF0). If the analog input pins are changed during A/D conversion, therefore, the A/D conversion result and the conversion end interrupt request flag may reflect the previous analog input immediately before rewriting ADML0.
Page 186: Chapter 11 Serial Interface 20
CHAPTER 11 SERIAL INTERFACE 20 11.1 Serial Interface 20 Functions Serial interface 20 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode Operation stop mode This mode is used when serial transfer is not performed. Power consumption is minimized in this mode. Asynchronous serial interface (UART) mode This mode is used to send and receive the one byte of data that follows a start bit.
Page 187: Block Diagram Of Serial Interface 20
CSIE20 DIR20 CSCK20 SI20/P22 /RxD20 Output latch (P21) SO20/P21 /TxD20 Port mode register (PM21) Detection of stop bit Receive data counter Detection Output latch of start bit (P20) SCK20/P20 /ASCK20 Port mode Clock phase register (PM20) control Note See Figure11-2 for the configuration of the baud rate generator. Figure 11-1.
Page 188 Figure 11-2. Block Diagram of Baud Rate Generator 20 Clock for receive detection Transmit shift clock Receive shift clock TXE20 RXE20 CSIE20 Receive detection Transmit clock counter (3 bits) Receive clock counter (3 bits) TPS203 TPS202 TPS201 TPS200 Baud rate generator control register 20 (BRGC20) ASCK20/SCK20/P20 Internal bus...
Page 189 CHAPTER 11 SERIAL INTERFACE 20 Transmit shift register 20 (TXS20) TXS20 is a register in which transmit data is prepared. The transmit data is output from TXS20 bit-serially. When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmit data. Writing data to TXS20 triggers transmission.
Page 190: Serial Interface 20 Control Registers
11.3 Serial Interface 20 Control Registers Serial interface 20 is controlled by the following six registers. • Serial operation mode register 20 (CSIM20) • Asynchronous serial interface mode register 20 (ASIM20) • Asynchronous serial interface status register 20 (ASIS20) • Baud rate generator control register 20 (BRGC20) •...
Page 191: Format Of Asynchronous Serial Interface Mode Register 20
Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is used to make the settings related to asynchronous serial interface mode. ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. Figure 11-4. Format of Asynchronous Serial Interface Mode Register 20 Symbol <7>...
Page 192: Serial Interface 20 Operation Mode Settings
Table 11-2. Serial Interface 20 Operation Mode Settings Operation stop mode ASIM20 CSIM20 PM22 TXE20 RXE20 CSIE20 DIR20 CSCK20 Note 1 × × × Other than above 3-wire serial I/O mode ASIM20 CSIM20 PM22 TXE20 RXE20 CSIE20 DIR20 CSCK20 Note 2 Other than above Asynchronous serial interface mode ASIM20...
Page 193: Format Of Asynchronous Serial Interface Status Register 20
CHAPTER 11 SERIAL INTERFACE 20 Asynchronous serial interface status register 20 (ASIS20) ASIS20 indicates the type of a reception error, if it occurs while asynchronous serial interface mode is set. ASIS20 is set with a 1-bit or 8-bit memory manipulation instruction. The contents of ASIS20 are undefined in 3-wire serial I/O mode.
Page 194: Format Of Baud Rate Generator Control Register 20
Baud rate generator control register 20 (BRGC20) BRGC20 is used to specify the serial clock for serial interface 20. BRGC20 is set with an 8-bit memory manipulation instruction. RESET input sets BRGC20 to 00H. Figure 11-6. Format of Baud Rate Generator Control Register 20 Symbol BRGC20 TPS203 TPS202 TPS201 TPS200...
Page 195: Example Of Relationship Between System Clock And Baud Rate
CHAPTER 11 SERIAL INTERFACE 20 The baud rate transmit/receive clock to be generated is either a divided system clock signal, or a signal obtained by dividing the clock input to the ASCK20 pin. (a) Generation of UART baud rate transmit/receive clock form system clock The transmit/receive clock is generated by dividing the system clock.
Page 196 (b) Generation of UART baud rate transmit/receive clock from external clock input to ASCK20 pin The transmit/receive clock is generated by dividing the clock input from the ASCK20 pin. The baud rate of a clock generated from the clock input to the ASCK20 pin is estimated by using the following expression.
Page 197: Serial Interface 20 Operation
11.4 Serial Interface 20 Operation Serial interface 20 provides the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 11.4.1 Operation stop mode In operation stop mode, serial transfer is not executed, thereby reducing the power consumption. P20/SCK20/ASCK20, P21/SO20/TxD20, and P22/SI20/RxD20 pins can be used as normal I/O ports.
Page 198 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. Symbol <7> <6> ASIM20 TXE20 RXE20 PS201 TXE20 Transmit operation stopped Transmit operation enabled RXE20 Receive operation stopped Receive operation enabled Caution Bits 0 and 1 must be set to 0.
Page 199: Asynchronous Serial Interface (Uart) Mode
11.4.2 Asynchronous serial interface (UART) mode In this mode, the one-byte data following the start bit is transmitted/received, enabling full-duplex communication. This device incorporates a UART-dedicated baud rate generator that enables communications at the desired baud rate. In addition, the baud rate can also be defined by dividing the clock input to the ASCK20 pin. The UART-dedicated baud rate generator also can output the 31.25 Kbps baud rate that complies with the MIDI standard.
Page 200 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. Symbol <7> <6> ASIM20 TXE20 RXE20 PS201 TXE20 Transmit operation stopped Transmit operation enabled RXE20 Receive operation stopped Receive operation enabled PS201...
Page 201 (c) Asynchronous serial interface status register 20 (ASIS20) ASIS20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIS20 to 00H. Symbol ASIS20 PE20 No parity error occurred A parity error occurred (when the transmit parity and receive parity did not match) FE20 No framing error occurred A framing error occurred (when stop bit was not detected)
Page 202 (d) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input sets BRGC20 to 00H. Symbol BRGC20 TPS203 TPS202 TPS201 TPS203 TPS202 TPS201 Other than above Note Can only be used in the UART mode. Cautions 1.
Page 203: Example Of Relationship Between System Clock And Baud Rate
CHAPTER 11 SERIAL INTERFACE 20 Table 11-5. Example of Relationship Between System Clock and Baud Rate Baud Rate (bps) 1,200 2,400 4,800 9,600 19,200 38,400 76,800 Caution Do not select n = 1 during operation at f rated range. (ii) Generation of baud rate transmit/receive clock from external clock input to ASCK20 pin The transmit/receive clock is generated by dividing the clock input from the ASCK20 pin.
Page 204: Format Of Asynchronous Serial Interface Transmit/Receive Data
Communication operation (a) Data format The transmit/receive data format is as shown in Figure 11-7. One data frame consists of a start bit, character bits, parity bit, and stop bit(s). The specification of character bit length in one data frame, parity selection, and specification of stop bit length is carried out using asynchronous serial interface mode register 20 (ASIM20).
Page 205 CHAPTER 11 SERIAL INTERFACE 20 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected.
Page 206: Asynchronous Serial Interface Transmission Completion Interrupt Timing
(c) Transmission A transmit operation is started by writing transmit data to transmit shift register 20 (TXS20). The start bit, parity bit, and stop bit(s) are added automatically. When the transmit operation starts, the data in TXS20 is shifted out, and when TXS20 is empty, a transmission completion interrupt (INTST20) is generated.
Page 207: Asynchronous Serial Interface Reception Completion Interrupt Timing
CHAPTER 11 SERIAL INTERFACE 20 (d) Reception When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is set (1), a receive operation is enabled and sampling of the RxD20 pin input is performed. RxD20 pin input sampling is performed using the serial clock specified by BRGC20. When the RxD20 pin input becomes low, the 3-bit counter starts counting, and when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output.
Page 208: Receive Error Timing
(e) Receive errors The following three errors may occur during a receive operation: a parity error, framing error, and overrun error. After data reception, an error flag is set in asynchronous serial interface status register 20 (ASIS20). Receive error causes are shown in Table 11-7. It is possible to determine what kind of error occurred during reception by reading the contents of ASIS20 in the reception error interrupt servicing (see Table 11-7 and Figure 11-10).
Page 209 CHAPTER 11 SERIAL INTERFACE 20 (f) Reading receive data When the reception completion interrupt (INTSR20) occurs, receive data can be read by reading the value of receive buffer register 20 (RXB20). To read the receive data stored in receive buffer register 20 (RXB20), read while reception is enabled (RXE20 = 1).
Page 210 Cautions related to UART mode (a) When bit 7 (TXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during transmission, be sure to set transmit shift register 20 (TXS20) to FFH, then set TXE20 to 1 before executing the next transmission. (b) When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during reception, receive buffer register 20 (RXB20) and the receive completion interrupt (INTSR20) are as follows.
Page 211: 3-Wire Serial I/O Mode
11.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75XL Series, 78K Series, and 17K Series. Communication is performed using three lines: a serial clock (SCK20), serial output (SO20), and serial input (SI20).
Page 212 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. When 3-wire serial I/O mode is selected, ASIM20 must be set to 00H. Symbol <7> <6>...
Page 213 (c) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input sets BRGC20 to 00H. Symbol BRGC20 TPS203 TPS202 TPS201 TPS203 TPS202 TPS201 Other than above Caution When writing to BRGC20 during a communication operation, the baud rate generator output is disrupted and communications cannot be performed normally.
Page 214: Wire Serial I/O Mode Timing
Communication operation In 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. received bit by bit in synchronization with the serial clock. Transmit shift register 20 (TXS20/SIO20) and receive shift register 20 (RXS20) shift operations are performed in synchronization with the fall of the serial clock (SCK20). Then transmit data is held in the SO20 latch and output from the SO20 pin.
Page 215 CHAPTER 11 SERIAL INTERFACE 20 Figure 11-11. 3-Wire Serial I/O Mode Timing (2/2) (ii) Slave operation timing (CSCK20=1) SIO20 write SCK20 SI20 SO20 Note INTCSI20 Note The value of the last bit previously output is output. Transfer start Serial transfer is started by setting transfer data to transmit shift register 20 (TXS20/SIO20) when the following two conditions are satisfied.
Page 216: Chapter 12 Serial Interface 1A0
CHAPTER 12 SERIAL INTERFACE 1A0 12.1 Function of Serial Interface 1A0 Serial interface 1A0 has the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function Operation stop mode This mode is used when serial transfer will not be performed.
Page 217: Configuration Of Serial Interface 1A0
12.2 Configuration of Serial Interface 1A0 Serial interface 1A0 includes the following hardware. Table 12-1. Configuration of Serial Interface 1A0 Item Registers Serial I/O shift register 1A0 (SIO1A0) Automatic data transmit/receive address pointer 0 (ADTP0) Control registers Serial operation mode register 1A0 (CSIM1A0) Automatic data transmit/receive control register 0 (ADTC0) Automatic data transmit/receive interval specification register 0 (ADTI0) Port mode register 2 (PM2)
Page 218 Serial I/O shift register 1A0 (SIO1A0) This is an 8-bit register used to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO1A0 is set with an 8-bit memory manipulation instruction. When the value in bit 7 (CSIE10) of serial operation mode register 1A0 (CSIM1A0) is 1, writing data to SIO1A0 starts a serial operation.
Page 219: Control Registers For Serial Interface 1A0
12.3 Control Registers for Serial Interface 1A0 Serial interface 1A0 is controlled by the following five registers. • Serial operation mode register 1A0 (CSIM1A0) • Automatic data transmit/receive control register 0 (ADTC0) • Automatic data transmit/receive interval specification register 0 (ADTI0) •...
Page 220: Format Of Serial Operation Mode Register 1A0
Figure 12-2. Format of Serial Operation Mode Register 1A0 Symbol <7> <5> CSIM1A0 CSIE10 DIR10 ATE0 CSIE10 Shift register operation Operation stopped Operation enabled DIR10 ATE0 3-wire serial mode 3-wire serial mode with automatic transmit/receive function LSCK10 SCK10 is used as port (P23) when CSIE10 = 0. SCK10 is used for clock output when CSIE10 = 1.
Page 221: Format Of Automatic Data Transmit/Receive Control Register 0
Automatic data transmit/receive control register 0 (ADTC0) This register sets automatic reception enable/disable, the operation mode, and displays the state of automatic transmit/receive control. ADTC0 is set via a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 12-3.
Page 222: Format Of Automatic Data Transmit/Receive Interval Specification Register 0
Automatic data transmit/receive interval specification register 0 (ADTI0) This register sets the automatic data transmit/receive function data transfer interval. ADTI0 is set via a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 12-4. Format of Automatic Data Transmit/Receive Interval Specification Register 0 (1/2) Symbol <7>...
Page 223 Figure 12-4. Format of Automatic Data Transmit/Receive Interval Specification Register 0 (2/2) Symbol <7> ADTI0 ADTI07 ADTI04 ADTI03 ADTI02 Notes 1. The interval time depends only on the CPU processing. 2. The data transfer interval time is found from the following expressions (n: Value set to ADTI00 to ADTI04).
Page 224: Serial Interface 1A0 Operation
12.4 Serial Interface 1A0 Operation Serial interface 1A0 provides the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 12.4.1 Operation stop mode In operation stop mode, serial transfer is not executed, thereby reducing the power consumption. The P23/SCK10, P24/SO10, and P25/SI10 pins can be used as normal I/O ports.
Page 225: 3-Wire Serial I/O Mode
12.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75XL Series, 78K Series, and 17K Series. Communication is performed using three lines: a serial clock (SCK10), serial output (SO10), and serial input (SI10).
Page 226 Symbol <7> <5> CSIM1A0 CSIE10 DIR10 ATE0 CSIE10 Shift register operation Operation stopped Operation enabled DIR10 ATE0 3-wire serial mode 3-wire serial mode with automatic transmit/receive function LSCK10 SCK10 is used as port (P23) when CSIE10 = 0. SCK10 is used for clock output when CSIE10 = 1. SCK10 is fixed to high-level output when CSIE10 = 0.
Page 227: Wire Serial I/O Mode Timing
CHAPTER 12 SERIAL INTERFACE 1A0 Communication operation In 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. transmitted/received bit by bit in synchronization with the serial clock. Serial I/O shift register 1A0 (SIO1A0) shift operations are performed in synchronization with the fall of the serial clock (SCK10).
Page 228 CHAPTER 12 SERIAL INTERFACE 1A0 Figure 12-5. 3-Wire Serial I/O Mode Timing (2/2) (ii) Slave operation timing SIO1A0 write SCK10 SI10 SO10 Note INTCSI10 Note The value of the last bit previously output is output. User’s Manual U15331EJ4V1UD...
Page 229: Circuit Of Switching In Transfer Bit Order
CHAPTER 12 SERIAL INTERFACE 1A0 MSB/LSB switching as the start bit In the 3-wire serial I/O mode, transfer can be selected to start from the MSB or LSB. Figure 12-6 shows the configuration of serial I/O shift register 1A0 (SIO1A0) and the internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form.
Page 230: 3-Wire Serial I/O Mode With Automatic Transmit/Receive Function
12.4.3 3-wire serial I/O mode with automatic transmit/receive function This 3-wire serial I/O mode is used for transmission/reception of a maximum of 16-byte data without the use of software. Once transfer is started, the set number of bytes of data prestored in the RAM can be transmitted, and the set number of bytes of data can be received and stored in the RAM.
Page 231 Symbol <7> <5> CSIM1A0 CSIE10 DIR10 ATE0 CSIE10 Shift register operation Operation stopped Operation enabled DIR10 ATE0 3-wire serial mode 3-wire serial mode with automatic transmit/receive function LSCK10 SCK10 is used as port (P23) when CSIE10 = 0. SCK10 is used for clock output when CSIE10 = 1. SCK10 is fixed to high-level output when CSIE10 = 0.
Page 232 (b) Automatic data transmit/receive control register 0 (ADTC0) ADTC0 is set via a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Symbol <7> <6> ADTC0 ARLD0 Note 2 Reception disabled Reception enabled ARLD0 One-shot mode Repeat mode TRF0 Detection of termination of automatic transmission/reception (this bit is set to 0 upon suspension of automatic...
Page 233 (c) Automatic data transmit/receive interval specification register 0 (ADTI0) ADTI0 is set via a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Symbol <7> ADTI0 ADTI07 ADTI07 No control of interval by ADTI00 to ADTI04 Control of interval by ADTI00 to ADTI04 ADTI04 ADTI03...
Page 234 Symbol <7> ADTI0 ADTI07 ADTI04 ADTI03 ADTI02 Notes 1. The interval time depends only on the CPU processing. 2. The data transfer interval time is found from the following expressions (n: Value set to ADTI00 to ADTI04). <1> n = 0 Interval time = <2>...
Page 235 CHAPTER 12 SERIAL INTERFACE 1A0 Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FFA0H of buffer RAM (up to FFAFH). The transmit data should be in the order from higher address to lower address. <2>...
Page 236: Basic Transmit/Receive Mode Operation Timing
Communication operation (a) Basic transmit/receive mode This transmit/receive mode is the same as the 3-wire serial I/O mode in which the specified number of data are transmitted/received in 8-bit units. Serial transfer is started when any data is written to serial I/O shift register 1A0 (SIO1A0) while bit 7 (CSIE10) of serial operation mode register 1A0 (CSIM1A0) is set to 1.
Page 237: Basic Transmit/Receive Mode Flowchart
CHAPTER 12 SERIAL INTERFACE 1A0 Figure 12-8. Basic Transmit/Receive Mode Flowchart Start Write transmit data in buffer RAM Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Set the transmission/reception operation interval time in ADTI0 Write any data to SIO1A0 (Start trigger) Write transmit data from...
Page 238 In 6-byte transmission/reception (bit 6 (ARLD0) and bit 7 (RE0) of automatic data transmit/receive control register 0 (ADTC0) = 0, and 1, respectively) in basic transmit/receive mode, buffer RAM operates as follows. (i) Before transmission/reception (refer to Figure 12-9 (a)) After any data has been written to SIO1A0 (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1A0.
Page 239: Buffer Ram Operation In 6-Byte Transmission/Reception (In Basic Transmit/Receive Mode)
CHAPTER 12 SERIAL INTERFACE 1A0 Figure 12-9. Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) (2/2) (b) 4th byte transmission/reception FFAFH Receive data 1 (R1) FFA5H Receive data 2 (R2) Receive data 3 (R3) Transmit data 4 (T4) Transmit data 5 (T5) Transmit data 6 (T6) FFA0H...
Page 240: Basic Transmit Mode Operation Timing
(b) Basic transmit mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer is started when any data is written to serial I/O shift register 1A0 (SIO1A0) while bit 7 (CSIE10) of serial operation mode register 1A0 (CSIM1A0) is set to 1, and bit 7 (RE0) of automatic data transmit/receive control register 0 (ADTC0) is set to 0.
Page 241: Basic Transmit Mode Flowchart
CHAPTER 12 SERIAL INTERFACE 1A0 Figure 12-11. Basic Transmit Mode Flowchart Start Write transmit data in buffer RAM Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Set the transmission/reception operation interval time in ADTI0 Write any data to SIO1A0 (Start trigger) Write transmit data from...
Page 242: Buffer Ram Operation In 6-Byte Transmission (In Basic Transmit Mode)
In 6-byte transmission (bit 6 (ARLD0) and bit 7 (RE0) of automatic data transmit/receive control register 0 (ADTC0) are 0) in basic transmit mode, buffer RAM operates as follows. (i) Before transmission (refer to Figure 12-12 (a)) After any data has been written to SIO1A0 (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1A0.
Page 243 CHAPTER 12 SERIAL INTERFACE 1A0 Figure 12-12. Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) (2/2) (b) 4th byte transmission point FFAFH FFA5H Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) Transmit data 4 (T4) Transmit data 5 (T5) FFA0H Transmit data 6 (T6)
Page 244: Repeat Transmit Mode Operation Timing
(c) Repeat transmit mode In this mode, data stored in the buffer RAM is transmitted repeatedly. Serial transfer is started by writing any data to serial shift I/O register 1A0 (SIO1A0) when bit 7 (CSIE10) of serial operation mode register 1A0 (CSIM1A0) is set to 1, and bit 7 (RE0) of automatic data transmit/receive control register 0 (ADTC0) is set to 0.
Page 245: Repeat Transmit Mode Flowchart
CHAPTER 12 SERIAL INTERFACE 1A0 Figure 12-14. Repeat Transmit Mode Flowchart Start Write transmit data in buffer RAM Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Set the transmission/reception operation interval time in ADTI0 Write any data to SIO1A0 (Start trigger) Write transmit data from...
Page 246: Buffer Ram Operation In 6-Byte Transmission (In Repeat Transmit Mode)
In 6-byte transmission (bit 6 (ARLD0) and bit 7 (RE0) of automatic data transmit/receive control register 0 (ADTC0) are 1 and 0, respectively) in repeat transmit mode, buffer RAM operates as follows. (i) Before transmission (refer to Figure 12-15 (a)) After any data has been written to SIO1A0 (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1A0.
Page 247 CHAPTER 12 SERIAL INTERFACE 1A0 Figure 12-15. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) (2/2) (c) Upon completion of transmission of 6 bytes FFAFH FFA5H Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) Transmit data 4 (T4) Transmit data 5 (T5) FFA0H...
Page 248: Automatic Transmission/Reception Suspension And Restart
(d) Automatic transmission/reception suspension and restart Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE10) of serial operation mode register 1A0 (CSIM1A0) to 0. During 8-bit data transfer, the transmission/reception is not suspended if bit 7 (CSIE10) is set to 0. It is suspended upon completion of 8-bit data transfer.
Page 249: Interval Time Of Automatic Transmission/Reception
CHAPTER 12 SERIAL INTERFACE 1A0 Timing of interrupt request signal generation The interrupt request signal is generated in synchronization with the timing shown in Table 12-2. Table 12-2. Timing of Interrupt Request Signal Generation Operation Mode Single mode Master mode Slave mode Repeat transmit mode Interval time of automatic transmission/reception...
Page 250: Chapter 13 Lcd Controller/Driver
CHAPTER 13 LCD CONTROLLER/DRIVER 13.1 LCD Controller/Driver Functions The functions of the LCD controller/driver of the Automatic output of segment and common signals based on automatic display data memory read Two different display modes: • 1/3 duty (1/3 bias) • 1/4 duty (1/3 bias) Four different frame frequencies, selectable in each display mode 16 to 28 segment signal outputs (S0 to S15, S16 to S27 4 common signal outputs (COM0 to COM3)
Page 251: Correspondence With Lcd Display Ram
CHAPTER 13 LCD CONTROLLER/DRIVER The correspondence with the LCD display RAM is shown in Figure 13-1 below. Figure 13-1. Correspondence with LCD Display RAM Address FA1BH FA1AH FA19H FA18H FA17H FA16H FA15H FA14H FA13H FA12H FA11H FA10H FA0FH FA0EH FA0DH FA0CH FA0BH FA0AH...
Page 252: Lcd Controller/Driver Block Diagram
LCD clock control LCD display mode register 0 (LCDC0) register 0 (LCDM0) LCDC03 LCDC02 LCDC01 LCDC00 LCDON0 VAON0 Prescaler LCDCL clock selector VAON0 Clock generator for boosting Booster circuit CAPH CAPL Figure 13-2. LCD Controller/Driver Block Diagram Internal bus LCD voltage boost control register 0 (LCDVA0) FA00H LIPS0...
Page 253: Registers Controlling Lcd Controller/Driver
CHAPTER 13 LCD CONTROLLER/DRIVER 13.3 Registers Controlling LCD Controller/Driver The LCD controller/driver is controlled by the following three registers. • LCD display mode register 0 (LCDM0) • LCD clock control register 0 (LCDC0) • LCD voltage boost control register 0 (LCDVA0) User’s Manual U15331EJ4V1UD...
Page 254: Format Of Lcd Display Mode Register 0
LCD display mode register 0 (LCDM0) LCDM0 specifies whether to enable display. It also specifies whether to enable booster circuit operation, segment pin/common pin output, and the display mode. LCDM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets LCDM0 to 00H.
Page 255: Format Of Lcd Clock Control Register 0
CHAPTER 13 LCD CONTROLLER/DRIVER LCD clock control register 0 (LCDC0) LCDC0 specifies the LCD source clock and LCD clock. The frame frequency is determined according to the LCD clock and number of time slices. LCDC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets LCDC0 to 00H.
Page 256: Format Of Lcd Voltage Boost Control Register 0
LCD voltage boost control register 0 (LCDVA0) LCDVA0 controls the voltage boost level during the voltage boost operation. LCDVA0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets LCDVA0 to 00H. Figure 13-5. Format of LCD Voltage Boost Control Register 0 Symbol LCDVA0 GAIN...
Page 257: Setting Lcd Controller/Driver
13.4 Setting LCD Controller/Driver Set the LCD controller/driver using the following procedure. <1> Set the LCD clock using LCD clock control register 0 (LCDC0). <2> Set the voltage boost level using LCD voltage boost control register 0 (LCDVA0). GAIN = 0: VLC0 = 4.5 V, VLC1 = 3 V, VLC2 = 1. 5 V GAIN = 1: VLC0 = 3 V, VLC1 = 2 V, VLC2 = 1 V <3>...
Page 258: Common And Segment Signals
13.6 Common and Segment Signals Each pixel of the LCD panel turns on when the potential difference between the corresponding common and segment signals becomes higher than a specific voltage (LCD drive voltage, V difference becomes lower than V Applying DC voltage to the common and segment signals for an LCD panel would deteriorate it. To avoid this problem, this LCD panel is driven with AC voltage.
Page 259: Common Signal Waveforms
CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-7. Common Signal Waveforms COMn (Three-time-slice mode) = 3 × T COMn (Four-time-slice mode) = 4 × T T: One LCD clock period : Frame frequency Figure 13-8. Voltages and Phases of Common and Segment Signals Common signal Segment signal User’s Manual U15331EJ4V1UD...
Page 260: Display Modes
13.7 Display Modes 13.7.1 Three-time-slice display example Figure 13-10 shows how a nine-digit LCD panel having the display pattern shown in Figure 13-9 is connected to the segment signals (S0 to S26) and the common signals (COM0 to COM2) of the example displays the data "123456.789"...
Page 261: Example Of Connecting Three-Time-Slice Lcd Panel
CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-10. Example of Connecting Three-Time-Slice LCD Panel FA00H FA10H x’: Can be used to store any data because there is no corresponding segment in the LCD panel. ×: Can always be used to store any data because the three-time-slice mode is being used. COM 3 Open COM 2...
Page 262: Three-Time-Slice Lcd Drive Waveform Examples (1/3 Bias Method)
Figure 13-11. Three-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method) COM0 COM1 COM2 COM0-S9 COM1-S9 COM2-S9 CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD +1/3V -1/3V +1/3V -1/3V +1/3V -1/3V...
Page 263: Four-Time-Slice Display Example
13.7.2 Four-time-slice display example Figure 13-13 shows how a 14-digit LCD panel having the display pattern shown in Figure 13-12 is connected to the segment signals (S0 to S27) and the common signals (COM0 to COM3) of the example displays the data "123456.78901234" in the LCD panel. (addresses FA00H to FA1BH) correspond to this display.
Page 264: Example Of Connecting Four-Time-Slice Lcd Panel
Figure 13-13. Example of Connecting Four-Time-Slice LCD Panel FA00H FA10H CHAPTER 13 LCD CONTROLLER/DRIVER COM 3 COM 2 COM 1 COM 0 S 10 S 11 S 12 S 13 S 14 S 15 S 16 S 17 S 18 S 19 S 20 S 21...
Page 265: Four-Time-Slice Lcd Drive Waveform Examples (1/3 Bias Method)
CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-14. Four-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method) COM0 COM1 COM2 COM3 COM0-S16 COM1-S16 Remark The waveforms of COM2-S16 and COM3-S16 are omitted. User’s Manual U15331EJ4V1UD +1/3V -1/3V +1/3V -1/3V...
Page 266: Supplying Lcd Drive Voltages
13.8 Supplying LCD Drive Voltages V µ PD789489 Subseries contains a booster circuit (×3 only) to generate a supply voltage to drive the LCD. The internal LCD reference voltage is output from the V the V pin and a voltage three times higher than that on V The LCD reference voltage (V ) can be specified by setting LCD boost control register 0 (LCDVA0).
Page 267: Chapter 14 Multiplier
14.1 Multiplier Function The multiplier has the following function. • Calculation of 8 bits × 8 bits = 16 bits 14.2 Multiplier Configuration 16-bit multiplication result storage register 0 (MUL0) This register stores the 16-bit result of multiplication. This register holds the result of multiplication after 16 CPU clocks have elapsed. MUL0 is set with a 16-bit memory manipulation instruction.
Page 268: Block Diagram Of Multiplier
Multiplication data register A (MRA0) 16-bit multiplication result storage register 0 (Master) (MUL0) 16-bit multiplication result storage register 0 (Slave) CHAPTER 14 MULTIPLIER Figure 14-1. Block Diagram of Multiplier Internal bus Multiplication data register B (MRB0) Counter value Selector 16-bit adder Internal bus User’s Manual U15331EJ4V1UD...
Page 269: Multiplier Control Register
14.3 Multiplier Control Register The multiplier is controlled by the following register. • Multiplier control register 0 (MULC0) Multiplier control register 0 (MULC0) MULC0 indicates the operating status of the multiplier after operation, as well as controls the multiplier. MULC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 270: Multiplier Operation
14.4 Multiplier Operation The multiplier of the µPD789489 Subseries can execute the calculation of 8 bits × 8 bits = 16 bits. Figure 14-3 shows the operation timing of the multiplier where MRA0 is set to AAH and MRB0 is set to D3H. <1>...
Page 271: Chapter 15 Remote Controller Receiver ( Μ Pd789489, 78F9489 Only)
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( 15.1 Remote Controller Receiver Functions The remote controller receiver uses the following remote controller modes. • Type A reception mode … Guide pulse (half clock) provided 15.2 Remote Controller Receiver Configuration The remote controller receiver includes the following hardware. Table 15-1.
Page 272: Block Diagram Of Remote Controller Receiver
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( Figure 15-1. Block Diagram of Remote Controller Receiver Noise RIN/P34 canceler RMEN RMIN Compare register RMGPHS RMDLS RMDH0S RMDH1S End-width select register (RMER) RMEN PRSEN RMIN RMCK1 RMCK0 Remote controller receive control register ( (1) Remote controller receive shift register (RMSR) This is an 8-bit register for reception of remote controller data.
Page 273 CHAPTER 15 REMOTE CONTROLLER RECEIVER ( (2) Remote controller receive data register (RMDR) This register holds the remote controller reception data. When the remote controller receive shift register (RMSR) overflows, the data in RMSR is transferred to RMDR. Bit 7 stores the last data, and bit 0 stores the first data.
Page 274 CHAPTER 15 REMOTE CONTROLLER RECEIVER ( (4) Remote controller receive GPHS compare register (RMGPHS) This register is used to detect the high level of a remote controller guide pulse (short side). RMGPHS is set with an 8-bit memory manipulation instruction. RESET input sets RMGPHS to 00H.
Page 275 CHAPTER 15 REMOTE CONTROLLER RECEIVER ( (8) Remote controller receive DH0S compare register (RMDH0S) This register is used to detect the high level of remote controller data 0 (short side). RMDH0S is set with an 8-bit memory manipulation instruction. RESET input sets RMDH0S to 00H. (9) Remote controller receive DH0L compare register (RMDH0L) This register is used to detect the high level of remote controller data 0 (long side).
Page 276 CHAPTER 15 REMOTE CONTROLLER RECEIVER ( (12) Remote controller receive end-width select register (RMER) This register determines the interval between the timing at which the INTREND signal is output. RMER is set with an 8-bit memory manipulation instruction. RESET input sets RMER to 00H. Counter INTREND Caution For RMER and all the remote controller receive compare registers (RMGPHS, RMGPHL,...
Page 277: Registers To Control Remote Controller Receiver
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( 15.3 Registers to Control Remote Controller Receiver The remote controller receiver is controlled by the following register. • Remote controller receive control register (RMCN) (1) Remote controller receive control register (RMCN) This register is used to enable/disable remote controller reception and to set the noise elimination width, clock internal division, input invert signal, and source clock.
Page 278 CHAPTER 15 REMOTE CONTROLLER RECEIVER ( Figure 15-3. Format of Remote Controller Receive Control Register (2/2) Symbol RMCN RMEN PRSEN RMCK1 RMCK0 (625 kHz) (313 kHz) (156 kHz) (32.768 kHz) Cautions 1. Always set bits 2 and 3 to 0. 2.
Page 279: Operation Of Remote Controller Receiver
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( 15.4 Operation of Remote Controller Receiver The following remote controller reception mode is used for this remote controller receiver. • Type A reception mode with guide pulse (half clock) 15.4.1 Format of type A reception mode Figure 15-4 shows the data format for type A.
Page 280: Operation Flow Of Type A Reception Mode
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( Figure 15-5. Operation Flow of Type A Reception Mode Start Set compare registers Operation enabled Guide pulse high level width OK? Generate INTGP Data low level width OK? Note Read RMDR Data high level width OK? Set data to RMSR Set data to all bits...
Page 281: Timing
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( 15.4.3 Timing Operation varies depending on the positions of the RIN input waveform below. (1) Guide pulse high level width determination Relationship Between RMGPHS/RMGPHL/Counter Counter < PMGPHS PMGPHS ≤ counter < PMGPHL PMGPHL ≤ counter (2) Data low level width determination Relationship Between RMDLS/RMDLL/Counter Counter <...
Page 282 CHAPTER 15 REMOTE CONTROLLER RECEIVER ( (3) Data high level width determination Relationship Between RMDH0S/RMDH0L/RMDH1S/RMDH1L/Counter Counter < RMDH0S RMDH0S ≤ counter < RMDH0L RMDH0L ≤ counter < RMDH1S RMDH1S ≤ counter < RMDH1L RMDH1L ≤ counter PD789489, 78F9489 ONLY) <1> <3>...
Page 283: Compare Register Setting
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( (4) End width determination Relationship Between RMER/Counter Counter < RMER RMER ≤ counter 15.4.4 Compare register setting This remote controller receiver has the following 9 types of compare registers. • Remote controller receive GPHS compare register (RMGPHS) •...
Page 284: Setting Example (Where N1 = 1, N2 = 2)
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( Figure 15-6. Setting Example (Where n1 = 1, n2 = 2) Clock RMGPHS/RMDH0S/RMDH1S RMGPHL/RMDH0L/RMDH1L RIN_1 RIN_2 (1) Formula for RMGPHS, RMDLS, RMDH0S, and RMDH1S × (1 − a/100) (2) Formula for RMGPHL, RMDLL, RMDH0L, and RMDH1L ×...
Page 285: Error Interrupt Generation Timing
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( 15.4.5 Error interrupt generation timing After the guide pulse has been detected normally, the INTRERR signal is generated under any of the following conditions. • Counter < RMDLS at the rising edge of RIN •...
Page 286: Generation Timing Of Intrerr Signal
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( Figure 15-7. Generation Timing of INTRERR Signal RMGPHL RMGPHS INTRERR INTRERR INTRERR INTRERR INTRERR INTRERR INTREND INTRERR INTRERR INTRERR PD789489, 78F9489 ONLY) RMDLL RMDH1L RMDH1S RMER RMDLS RMDH0L RMDH0S User’s Manual U15331EJ4V1UD Basic waveform Example 1 Counter <...
Page 287: Noise Elimination
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( 15.4.6 Noise elimination This remote controller receiver provides a function that supplies the signals input from the outside to the RIN pin after eliminating noise. Noise width can be eliminated by setting bit 5 (PRSEN) and bit 6 (NCW) of the remote controller receive control register (RMCN) as shown in Figure 15-2.
Page 288: Noise Elimination Operation Example
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( Figure 15-8. Noise Elimination Operation Example (1/2) (a) 1-clock noise elimination (PRSEN = 0, NCW = 0) Clock RIN (ideal) Noise Synchronization samp1 samp2 Internal RIN Delayed by 2 to 3 clocks Remark Internal RIN is a signal after synchronization and sampling are performed twice, and is therefore later than the actual signal input from the outside to the RIN pin by two to three clocks.
Page 289 CHAPTER 15 REMOTE CONTROLLER RECEIVER ( Figure 15-8. Noise Elimination Operation Example (2/2) (c) 2-clock noise elimination (PRSEN = 1, NCW = 0) Clock Clock divider RIN (ideal) Noise Synchronization samp1 samp2 Internal RIN Delayed by 4 to 6 clocks Remark Internal RIN is a signal after synchronization and sampling are performed twice, and is therefore later than the actual signal input from the outside to the RIN pin by 4 to 6 clocks.
Page 290: Chapter 16 Interrupt Functions
Tables 16-1 and 16-2. A standby release signal is generated. µ For the PD789488 and 78F9488, 5 external and 11 internal interrupt sources are incorporated as maskable interrupts. µ For the PD789489 and 78F9489, 6 external and 16 internal interrupt sources are incorporated as maskable interrupts.
Page 291 3. There is no interrupt source that applies to 000EH and 0026H to 002CH of vector table address. Remark Only one of the two watchdog timer interrupt (INTWDT) sources, non-maskable or maskable (internal), can be selected. CHAPTER 16 INTERRUPT FUNCTIONS µ PD789488, 78F9488) Interrupt Source Trigger Watchdog timer overflow (with Internal watchdog timer mode 1 selected)
Page 292 Table 16-2. Interrupt Sources ( Note 1 Interrupt Type Priority Name − Non-maskable INTWDT Maskable INTWDT INTP0 INTP1 INTP2 INTP3 INTRIN INTSR20 INTCSI20 INTCSI10 INTST20 INTWTI INTTM20 INTTM50 INTTM60 INTTM61 INTAD0 INTWT INTKR00 INTRERR INTGP INTREND INTDFULL INTKR01 Notes 1. Priority is the priority order when more than one maskable interrupt request is generated at the same time.
Page 293: Basic Configuration Of Interrupt Function
CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Interrupt request (B) Internal maskable interrupt Interrupt request (C) External maskable interrupt INTM0, INTM1, KRM00, KRM01 Interrupt Edge request detector INTM0: External interrupt mode register 0 INTM1: External interrupt mode register 1 KRM00:...
Page 294: Registers Controlling Interrupt Function
16.3 Registers Controlling Interrupt Function The following five types of registers are used to control the interrupt functions. • Interrupt request flag registers (IF0 to IF2) • Interrupt mask flag registers (MK0 to MK2) • External interrupt mode registers (INTM0 and INTM1) •...
Page 295: Format Of Interrupt Request Flag Registers
Interrupt request flag registers (IF0 to IF2) An interrupt request flag is set (1) when the corresponding interrupt request is generated, or when an instruction is executed. It is cleared (0) when the interrupt request is acknowledged, when the RESET signal is input, or when an instruction is executed.
Page 296: Format Of Interrupt Mask Flag Registers
Interrupt mask flag registers (MK0 to MK2) Interrupt mask flags are used to enable and disable the corresponding maskable interrupts. MK0 to MK2 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. Figure 16-3.
Page 297: Format Of External Interrupt Mode Registers
External interrupt mode registers (INTM0, INTM1) These registers are used to specify the valid edge for INTP0 to INTP3. INTM0 and INTM1 are set with an 8-bit memory manipulation instruction. RESET input sets these registers to 00H. Figure 16-4. Format of External Interrupt Mode Registers Symbol INTM0 ES21...
Page 298: Program Status Word Configuration
Program status word (PSW) The program status word is used to hold the instruction execution results and the current status of the interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to the PSW. The PSW can be read and written in 8-bit units, and can be manipulated by using bit manipulation instructions and dedicated instructions (EI and DI).
Page 299: Format Of Key Return Mode Register 00
Key return mode register 00 (KRM00) This register is used to set the pin that is to detect the key return signal (rising edge of port 0). KRM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 16-6.
Page 300: Format Of Key Return Mode Register 01
Key return mode register 01 (KRM01) ( This register is used to set the pin that is to detect the key return signal (falling edge of port 6). KRM01 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 16-8.
Page 301: Interrupt Servicing Operation
16.4 Interrupt Servicing Operation 16.4.1 Non-maskable interrupt request acknowledgment operation The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts. When the non-maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Page 302: Flow From Generation Of Non-Maskable Interrupt Request To Acknowledgment
Figure 16-10. Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment (watchdog timer mode (non-maskable interrupt Interrupt request is generated Interrupt servicing starts WDTM: Watchdog timer mode register WDT: Figure 16-11. Timing of Non-Maskable Interrupt Request Acknowledgment CPU processing Instruction WDTIF Figure 16-12.
Page 303: Maskable Interrupt Request Acknowledgment Operation
16.4.2 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt is acknowledged in the interrupt enabled status (when the IE flag is set to 1).
Page 304: Multiple Interrupt Servicing
Figure 16-14. Interrupt Request Acknowledgment Timing (Example: MOV A, r) Clock MOV A, r Interrupt If the interrupt request has generated an interrupt request flag (xxIFx) by the time the instruction clocks under execution, n clocks (n = 4 to 10), are n − 1, interrupt request acknowledgment processing will start following the completion of the instruction under execution.
Page 305: Example Of Multiple Interrupt Servicing
Figure 16-16. Example of Multiple Interrupt Servicing Example 1. Acknowledging multiple interrupts Main servicing IE = 0 INTxx The interrupt request INTyy is acknowledged during the servicing of interrupt INTxx and multiple interrupts are performed. Before each interrupt request is acknowledged, the EI instruction is issued and the interrupt request is enabled.
Page 306: Putting Interrupt Requests On Hold
16.4.4 Putting interrupt requests on hold If an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. Such instructions (interrupt request pending instructions) are as follows.
Page 307: Chapter 17 Standby Function
17.1 Standby Function and Configuration 17.1.1 Standby function The standby function is used to reduce the power consumption of the system and can be effected in the following two modes. HALT mode This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the CPU.
Page 308: Register Controlling Standby Function
17.1.2 Register controlling standby function The wait time after the STOP mode is released upon interrupt request generation until oscillation stabilizes is controlled by the oscillation stabilization time selection register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 309: Standby Function Operation
17.2 Standby Function Operation 17.2.1 HALT mode HALT mode The HALT mode is set by executing the HALT instruction. The operation statuses in the HALT mode are shown in the following table. Table 17-1. Operation Statuses in HALT Mode Item HALT Mode Operation Status During Main System Clock Operation Subsystem Clock...
Page 310: Releasing Halt Mode By Interrupt
Releasing HALT mode The HALT mode can be released by the following three sources. Release by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if interrupts are enabled to be acknowledged, vectored interrupt servicing is performed. If interrupts are disabled, the instruction at the next address is executed.
Page 311: Releasing Halt Mode By Reset Input
Release by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 17-3. Releasing HALT Mode by RESET Input HALT instruction RESET...
Page 312: Stop Mode
17.2.2 STOP mode Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction. Caution Because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset.
Page 313: Releasing Stop Mode By Interrupt
Releasing STOP mode The STOP mode can be released by the following two sources. Release by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if interrupts are enabled to be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization time has elapsed.
Page 314: Releasing Stop Mode By Reset Input
Release by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 17-5. Releasing STOP Mode by RESET Input STOP instruction RESET signal Operation mode Oscillation Clock Remark...
Page 315: Chapter 18 Reset Function
The following two operations are available to generate reset signals. (1) External reset input by RESET pin (2) Internal reset by watchdog timer program loop time detection External and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.
Page 316: Reset Timing By Reset Input
Figure 18-2. Reset Timing by RESET Input During normal operation RESET Internal reset signal Port pin Figure 18-3. Reset Timing by Overflow in Watchdog Timer During normal operation Overflow in watchdog timer Internal reset signal Port pin Figure 18-4. Reset Timing by RESET Input in STOP Mode STOP instruction execution During normal operation...
Page 317: Status Of Hardware After Reset
Table 18-1. Status of Hardware After Reset (1/2) Note 1 Program counter (PC) Stack pointer (SP) Program status word (PSW) Data memory General-purpose registers Note 3 Ports (P0 to P3, P5, P8 ) (output latches) Port mode registers (PM0 to PM3, PM5, PM8 Port function registers (PF7, PF8) Pull-up resistor option registers (PUB0 to PUB3) Processor clock control register (PCC)
Page 318 Table 18-1. Status of Hardware After Reset (2/2) Serial interface 1A0 Operation mode register (CSIM1A0) Shift register (SIO1A0) Buffer memory (SBMEM0 to SBMEMF) Automatic data transmit/receive control register (ADTC0) Automatic data transmit/receive address pointer (ADTP0) Automatic data transmit/receive transfer interval specification register (ADTI0) A/D converter Mode register (ADML0) Input channel specification register (ADS0)
Page 319: Chapter 19 Flash Memory Version
ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM version. µ PD789488 (mask ROM version). µ PD789489 (mask ROM version). µ...
Page 320: Flash Memory Characteristics
19.1 Flash Memory Characteristics Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL- PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the mounted on the target system (on-board). A flash memory program adapter (FA adapter), which is a target board used exclusively for programming, is also provided.
Page 321: Communication Mode
Note 1, 2, 4, 5 1 to 5 MHz Note 3 Note 5 5 MHz 4.91 or Note 2 5 MHz µ PD789488, 78F9488, 789489, 78F9489). User’s Manual U15331EJ4V1UD Pins Used Number of V Pulses Rate SI20/RxD20/P22 SO20/TxD20/P21 SCK20/ASCK20/ SI20/RxD20/P22...
Page 322: Example Of Connection With Dedicated Flash Programmer
Figure 19-3. Example of Connection with Dedicated Flash Programmer Dedicated flash programmer Dedicated flash programmer Dedicated flash programmer Notes 1. When the system clock is supplied from the dedicated flash programmer, connect the CLK pin with X1 pin and disconnect the on-board resonator. When using the clock of the on-board resonator, do not connect the CLK pin.
Page 323: Pin Connection List
If Flashpro III/Flashpro IV is used as a dedicated flash programmer, the following signals are generated for the µ PD78F9488 and 78F9489. For details, refer to the manual of Flashpro III/Flashpro IV. Signal Name Pin Function VPP1 Output Write voltage −...
Page 324: On-Board Pin Processing
19.1.3 On-board pin processing When performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. An on-board function that allows switching between normal operation mode and flash memory programming mode may be required in some cases. <V pin>...
Page 325: Signal Conflict (Input Pin Of Serial Interface)
CHAPTER 19 FLASH MEMORY VERSION Signal conflict If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device or set the other device to the output high impedance status.
Page 326: Signal Conflict (Reset Pin)
<RESET pin> If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator. If the reset signal is input from the user system in the flash memory programming mode, a normal programming operation cannot be performed.
Page 327: Connection Of Adapter For Flash Writing
19.1.4 Connection of adapter for flash writing The following figure shows an example of recommended connection when the adapter for flash writing is used. Figure 19-8. Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CHAPTER 19 FLASH MEMORY VERSION µ...
Page 328: Wiring Example For Flash Writing Adapter With 3-Wire Serial I/O With Handshake
Figure 19-9. Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O with Handshake 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CHAPTER 19 FLASH MEMORY VERSION µ...
Page 329: Wiring Example For Flash Writing Adapter With Uart
CHAPTER 19 FLASH MEMORY VERSION Figure 19-10. Wiring Example for Flash Writing Adapter with UART 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 µ PD78F9488, µ PD78F9489 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VDD2 (LVDD) CLKOUT RESET VPP RESERVE/HS WRITER INTERFACE...
Page 330: Cautions On Pd78F9488 And 78F9489
µ 19.2 Cautions on PD78F9488 and 78F9489 When using HALT mode with subclock multiplied by four Observe the following constraints when using the flash version ( mode with the subclock multiplied by 4 as the CPU clock. • Be sure to insert the following number of NOP instructions immediately after the HALT instruction. Operating Temperature = −40 to +45°C = −40 to +80°C...
Page 331: Chapter 20 Mask Options
µ PD789488 and 789489 have the following mask options. • Pin function The segment pins of the LCD and port 7 (input port) can be selected in 1-bit units. <1> S (16 + n) <2> P7n (n = 0 to 3) The segment pins of the LCD and port 8 (I/O port) can be selected in 1-bit units.
Page 332: Chapter 21 Instruction Set
This chapter lists the instruction set of the language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E). 21.1 Operation 21.1.1 Operand identifiers and description methods Operands are described in the “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details).
Page 333: Description Of "Operation" Column
21.1.2 Description of “Operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW: Program status word Carry flag...
Page 334: Operation List
21.2 Operation List Mnemonic Operands r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] [DE], A A, [HL] [HL], A A, [HL+byte] [HL+byte], A A, X...
Page 335 Mnemonic Operands MOVW rp, #word AX, saddrp saddrp, AX AX, rp rp, AX XCHW AX, rp A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte] ADDC A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte] A, #byte...
Page 336 Mnemonic Operands SUBC A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte] A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte] A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte] A, #byte...
Page 337 Mnemonic Operands A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte] ADDW AX, #word SUBW AX, #word CMPW AX, #word saddr saddr INCW DECW A, 1 A, 1 RORC A, 1 ROLC A, 1 SET1 saddr.bit sfr.bit A.bit...
Page 338 Mnemonic Operands CALL !addr16 CALLT [addr5] RETI PUSH MOVW SP, AX AX, SP !addr16 $addr16 $saddr16 $saddr16 $saddr16 $saddr16 saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 DBNZ B, $addr16 C, $addr16 saddr, $addr16 HALT STOP...
Page 339: Instructions Listed By Addressing Type
21.3 Instructions Listed by Addressing Type 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte 1st Operand Note ADDC Note SUBC ADDC SUBC B, C saddr ADDC SUBC...
Page 340 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word 1st Operand ADDW SUBW CMPW MOVW saddrp Note Only when rp = BC, DE, or HL. Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 1st Operand A.bit sfr.bit saddr.bit...
Page 341 Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand 1st Operand Basic Instructions Compound Instructions Other instructions RET, RETI, NOP, EI, DI, HALT, STOP CHAPTER 21 INSTRUCTION SET !addr16 [addr5] CALL CALLT User’s Manual U15331EJ4V1UD $addr16 DBNZ...
Page 342: Chapter 22 Electrical Specifications ( Μ Pd789488, 78F9488, 789489, 78F9489)
1.8 V 1.8 V Only when selected by a mask option or port function register 6.5 V or less µ PD789488, 78F9488, 789489, 78F9489) Conditions = AV µ PD78F9488, 78F9489 only, Note 1 P00 to P07, P10, P11, P20 to P25, P30 to...
Page 343 Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. µ PD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD...
Page 344 For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. µ PD789488, 78F9488, 789489, 78F9489) = –40 to +85°C, V = 1.8 to 5.5 V) Parameter...
Page 345 For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. µ PD789488, 78F9488, 789489, 78F9489) = –40 to +85°C, V = 1.8 to 5.5 V) Parameter...
Page 346 Note Only when selected by a mask option or port function register Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. µ PD789488, 78F9488, 789489, 78F9489) = 1.8 to 5.5 V) (1/6) Conditions = 2.7 to 5.5 V = 1.8 to 5.5 V N-ch open = 2.7 to 5.5 V...
Page 347 Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. µ PD789488, 78F9488, 789489, 78F9489) = 1.8 to 5.5 V) (2/6) Conditions P00 to P07, P10, P11, P20 to P25, P30 to P34,...
Page 348 8. This is the total current that flows to V Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. µ PD789488, 78F9488, 789489, 78F9489) = 1.8 to 5.5 V) (3/6) Conditions Note 2 = 5.0 V ±10% Note 3 = 3.0 V ±10%...
Page 349 8. This is the total current that flows to V Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. µ PD789488, 78F9488, 789489, 78F9489) = 1.8 to 5.5 V) (4/6) Conditions Note 2 = 5.0 V ±10% Note 3 = 3.0 V ±10%...
Page 350 8. This is the total current that flows to V Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. µ PD789488, 78F9488, 789489, 78F9489) = 1.8 to 5.5 V) (5/6) Conditions Note 2 = 5.0 V ±10% Note 3 = 3.0 V ±10%...
Page 351 8. This is the total current that flows to V Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. µ PD789488, 78F9488, 789489, 78F9489) = 1.8 to 5.5 V) (6/6) Conditions Note 2 = 5.0 V ±10% Note 3 = 3.0 V ±10%...
Page 352 KR0 to KR7( level width KR00 to KR07, KR10 to KR17 ( 78F9489) RESET low-level width µ PD789488, 78F9488, 789489, 78F9489) = 1.8 to 5.5 V) Conditions = 2.7 to 5.5 V = 1.8 to 5.5 V Original = 1.8 to 5.5 V...
Page 353 Note R and C are the load resistance and load capacitance of the SO20 output line. (c) UART mode (dedicated baud rate generator output) Parameter Symbol Transfer rate µ PD789488, 78F9488, 789489, 78F9489) = –40 to +85°C, V = 1.8 to 5.5 V) Conditions = 2.7 to 5.5 V = 1.8 to 5.5 V = 2.7 to 5.5 V...
Page 354 KCY3 ASCK20 high-/low-level width Transfer rate ASCK20 rise/fall time µ PD789488, 78F9488, 789489, 78F9489) Conditions = 2.7 to 5.5 V = 1.8 to 5.5 V = 2.7 to 5.5 V = 1.8 to 5.5 V = 2.7 to 5.5 V = 1.8 to 5.5 V...
Page 355 KSO5 to SO10 output Note R and C are the load resistance and load capacitance of the SO10 output line. µ PD789488, 78F9488, 789489, 78F9489) = –40 to +85°C, V = 1.8 to 5.5 V) Conditions = 2.7 to 5.5 V = 1.8 to 5.5 V...
Page 356 0.2V Clock Timing X1 input XT1 input Capture Input Timing CPT20 TMI Timing TMI60, TMI61 Interrupt Input Timing INTP0 to INTP3 µ PD789488, 78F9488, 789489, 78F9489) Point of measurement CPTH CPTL INTL User’s Manual U15331EJ4V1UD 0.8V 0.2V (MIN.) (MAX.) (MIN.) (MAX.)
Page 357 CHAPTER 22 ELECTRICAL SPECIFICATIONS ( Key Return Input Timing KR0 to KR7 µ ( PD789488, 78F9488) , KR00 to KR07, KR10 to KR17 µ ( PD789489, 78F9489) RESET Input Timing RESET Serial Transfer Timing 3-wire serial I/O mode: SCK10, SCK20...
Page 358 2.7 V ≤ AV 1.8 V ≤ AV Analog input voltage Note Excludes quantization error (±0.05%) Remark FSR: Full scale range µ PD789488, 78F9488, 789489, 78F9489) ≤ 5.5 V, AV = 0 V) Conditions ≤ 5.5 V < 4.5 V < 2.7 V ≤...
Page 359 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T Parameter Symbol Data retention power DDDR supply voltage Release signal set time SREL µ PD789488, 78F9488, 789489, 78F9489) = 1.8 to 5.5 V) Conditions Note 1 µ = 0.47 GAIN = 1 GAIN = 0 Note 1 µ...
Page 360 Notes 1. Use a resonator whose oscillation stabilizes within the oscillation stabilization wait time. 2. Selection of 2 stabilization time selection register (OSTS). Remark : Main system clock oscillation frequency µ PD789488, 78F9488, 789489, 78F9489) STOP mode Data retention mode DDDR STOP mode Data retention mode DDDR = –40 to +85°C, V...
Page 361 Unit erase time Total erase time Number of overwrites supply voltage Note Excludes current flowing through ports (including on-chip pull-up resistors) µ PD789488, 78F9488, 789489, 78F9489) = 10 to 40°C, V Symbol Conditions 2.7 V ≤ V ≤ 5.5 V 1.8 V ≤...
Page 362: Chapter 23 Characteristics Curves Of Lcd Controller/Driver
CHAPTER 23 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES) (1) Characteristics curves of voltage boosting stabilization time The following shows the characteristics curves of the time from the start of voltage boosting (VAON0 = 1) and the changes in the LCD output voltage (when GAIN is set as 1 (using the 3 V display panel)). LCD output voltage/Voltage boosting time 1000 1500...
Page 363 CHAPTER 23 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES) Temperature characteristics of LCD output voltage The following shows the temperature characteristics curves of LCD output voltage. LCD output voltage/Temperature (When GAIN = 1) −40 −30 −20 −10 LCD output voltage/Temperature (When GAIN = 0) −40 −30 −20...
Page 364: Chapter 24 Package Drawings
80-PIN PLASTIC QFP (14x14) NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. CHAPTER 24 PACKAGE DRAWINGS User’s Manual U15331EJ4V1UD detail of lead end ITEM MILLIMETERS 17.20±0.20 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06 0.13...
Page 365 CHAPTER 24 PACKAGE DRAWINGS 80-PIN PLASTIC TQFP (FINE PITCH) (12x12) NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. User’s Manual U15331EJ4V1UD detail of lead end ITEM MILLIMETERS 14.0±0.2 12.0±0.2 12.0±0.2 14.0±0.2 1.25 1.25...
Page 366: Chapter 25 Recommended Soldering Conditions
CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS µ PD789489 subseries should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website.
Page 367 CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS Table 25-1. Surface Mounting Type Soldering Conditions (2/3) µ PD78F9489GC-8BT: 80-pin plastic QFP (14x14) Soldering Method Interface reflow Package peak temperature: 235°C, Time:30 seconds max. (at 210°C or higher), Count: Twice or less, Exposure limit: 7 days 10 hours) Package peak temperature: 215°C, Time:40 seconds max.
Page 368 Caution Do not use different soldering methods together (except for partial heating). Remarks 1. Products that have the part numbers suffixed by "-A" are lead-free products. 2. For soldering methods and conditions other than those recommended above, contact an NEC Electronics sales representative.
Page 369: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the Figure A-1 shows development tools. • Support for PC98-NX Series Unless specified otherwise, the products supported by IBM PC/AT™ compatibles can be used in the PC98-NX Series.
Page 370: A-1 Development Tools
APPENDIX A DEVELOPMENT TOOLS Language processing software · Assembler package · C compiler package · Device file · C library source file Flash memory writing environment Flash programmer Flash memory writing adapter Flash memory Notes 1. C library source file is not included in the software package. 2.
Page 371: Software Package
A.1 Software Package SP78K0S Software tools for development of the 78K/0S Series are combined in this package. Software package The following tools are included. RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, and device files Part number: ×××× in the part number differs depending on the OS used Remark µ...
Page 372: Control Software
×××× in the part number differs depending on the host machine and operating system to be used. Remark µ S××××RA78K0S µ S××××CC78K0S ×××× AB13 PC-9800 series, IBM PC/AT compatible BB13 AB17 BB17 3P17 HP9000 series 700 3K17 SPARCstation µ S××××DF789488 µ...
Page 373: Debugging Tools (Hardware)
A.5 Debugging Tools (Hardware) IE-78K0S-NS In-circuit emulator for debugging hardware and software of an application system using the In-circuit emulator 78K/0S Series. Can be used with the integrated the debugger ID78K0S-NS. Used in combination with an AC adapter, emulation probe, and interface adapter for connecting the host machine.
Page 374: Debugging Tools (Software)
A.6 Debugging Tools (Software) ID78K0S-NS This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the Integrated debugger 78K/0S Series. The ID78K0S-NS is Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result.
Page 375: Appendix B Notes On Target System Design
APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figures B-1 to B-6 show the conditions when connecting the emulation probe to the conversion adapter or conversion socket. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system.
Page 376: B-2 Connection Conditions Of Target System (When Np-80Gc-Tq Is Used)
APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. Connection Conditions of Target System (When NP-80GC-TQ Is Used) Emulation board IE-789488-NS-EM1 24.8 mm 25 mm Figure B-3. Connection Conditions of Target System (When NP-H80GC-TQ Is Used) Emulation board IE-789488-NS-EM1 25.3 mm 25 mm Emulation probe NP-80GC-TQ...
Page 377: B-4 Distance Between In-Circuit Emulator And Conversion Adapter (80Gk)
APPENDIX B NOTES ON TARGET SYSTEM DESIGN (2) NP-80GK, NP-H80GK-TQ Figure B-4. Distance Between In-Circuit Emulator and Conversion Adapter (80GK) In-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A Emulation board IE-789488-NS-EM1 TGCN1 Emulation probe NP-80GK, NP-H80GK-TQ Note Distance when NP-80GK is used. When NP-H80GK-TQ is used, the distance is 370 mm. Note 170 mm User’s Manual U15331EJ4V1UD...
Page 378: B-5 Connection Conditions Of Target System (When Np-80Gk Is Used)
APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-5. Connection Conditions of Target System (When NP-80GK Is Used) Emulation board IE-789488-NS-EM1 23 mm 25 mm Figure B-6. Connection Conditions of Target System (When NP-H80GK-TQ Is Used) Emulation board IE-789488-NS-EM1 23 mm 10 mm Emulation probe NP-80GK...
Page 379: Appendix C Register Index
C.1 Register Index (Register Names in Alphabetic Order) A/D conversion result register 0 (ADCRL0) ... 174 A/D converter mode register 0 (ADML0) ... 176 Analog input channel specification register 0 (ADS0)... 177 Asynchronous serial interface mode register 20 (ASIM20)... 191 Asynchronous serial interface status register 20 (ASIS20)...
Page 380 APPENDIX C REGISTER INDEX LCD clock control register 0 (LCDC0) ...256 LCD display mode register 0 (LCDM0) ...256 LCD voltage boost control register 0 (LCDVA0) ...256 Multiplication data register A0 (MRA0) ...267 Multiplication data register B0 (MRB0) ...267 Multiplier control register 0 (MULC0) ...269 Oscillation stabilization time select register (OSTS) ...308 Port 0 (P0) ...77 Port 1 (P1) ...78...
Page 381 APPENDIX C REGISTER INDEX Remote controller receive end width select register (RMER) ... 276 Remote controller receive shift receive (RMSR)... 272 Remote controller shift register receive counter register (RMSCR) ... 273 16-bit capture register 20 (TCP20) ... 109 16-bit compare register 20 (CR20) ... 109 16-bit multiplication result storage register H (MUL0H) ...
Page 382: Register Index (Register Symbols Alphabetic Order)
C.2 Register Index (Register Symbols Alphabetic Order) ADCRL0: A/D conversion result register 0...174 ADML0: A/D converter mode register 0 ...176 ADS0: Analog input channel specification register 0 ...177 ADTC0: Automatic data transmit/receive control register 0 ...221 ADTI0: Automatic data transmit/receive interval specification register 0...222 ADTP0: Automatic data transmit/receive address pointer 0 ...218 ASIM20:...
Page 383 MUL0H: 16-bit multiplication result storage register H ... 267 MUL0L: 16-bit multiplication result storage register L... 267 MULC0: Multiplier control register 0... 269 OSTS: Oscillation stabilization time select register ... 308 Port 0 ... 77 Port 1 ... 78 Port 2 ... 79 Port 3 ...
Page 384 SIO1A0: Serial I/O shift register 1A0 ...218 SSCK: Subclock selection register ...100 TCA60: Carrier generator output control register 60 ...131 TCP20: 16-bit capture register 20 ...109 TM20: 16-bit timer counter 20 ...109 TM50: 8-bit timer counter 50 ...127 TM60: 8-bit timer counter 60 ...127 TM61: 8-bit timer counter 61 ...127 TMC20:...
Page 385: Appendix D Revision History
The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapters of each edition in which the revision was applied. Edition Major Revision from Previous Edition Correction of number of vectored interrupt sources in 1.7 Overview of Functions Change of V pin handling...
Page 386: Differences Between Μ Pd78F9488, 78F9489, And Mask Rom Version
VERSION CHAPTER 22 ELECTRICAL SPECIFICATIONS ( 78F9488) µ PD789489, 78F9489 CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET) µ APPENDIX A DEVELOPMENT TOOLS APPENDIX B NOTES ON TARGET SYSTEM DESIGN User’s Manual U15331EJ4V1UD (2/4) Applied to: PD789489, 78F9489 ONLY) µ PD789488, PD789489, 78F9489)
Page 387 Edition Major Revision from Previous Edition µ Change of descriptions of PD789489, 78F9489 • Change of status from under development to development completed • Change of the subseries name to “ Update of 1.5 78K/0S Series Lineup to latest version Modification of Figure 7-2 Block Diagram of Timer 50 Modification of Figure 7-3 Block Diagram of Timer 60 Modification of Figure 7-5 Block Diagram of Output control...
Page 388 CHAPTER 22 ELECTRICAL µ PD789489 and 78F9489 to SPECIFICATIONS ( 78F9488, 789489, 78F9489) µ CHAPTER 25 RECOMMENDED PD789489 and 78F9489 SOLDERING CONDITIONS Throughout CHAPTER 13 LCD CONTROLLER/DRIVER CHAPTER 19 FLASH MEMORY VERSION User’s Manual U15331EJ4V1UD (4/4) Applied to: µ PD789488,...

This manual is also suitable for:

Pd78f9488 Pd78f9489 Pd789489

NEC PD789488 User Manual

Chapter 1 General

Chapter 2 Pin Functions

Chapter 3 Cpu Architecture

Chapter 4 Port Functions

Chapter 5 Clock Generator

Chapter 6 16-Bit Timer 20

Chapter 7 8-Bit Timers 50, 60, and 61

Chapter 8 Watch Timer

Chapter 9 Watchdog Timer

Chapter 10 10-Bit A/D Converter

Chapter 11 Serial Interface 20

Chapter 12 Serial Interface 1A0

Chapter 13 Lcd Controller/Driver

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Summary of Contents for NEC PD789488