NEC PD78052 User Manual page 569

Instruction
Mnemonic
Group
CY, saddr.bit
CY, sfr.bit
AND1 CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
OR1 CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
XOR1 CY, A.bit
Bit
manipulate
CY, PSW. bit
CY, [HL].bit
saddr.bit
sfr.bit
SET1 A.bit
PSW.bit
[HL].bit
saddr.bit
sfr.bit
CLR1 A.bit
PSW.bit
[HL].bit
SET1 CY
CLR1 CY
NOT1 CY
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access.
2. When an area except the internal high-speed RAM area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
control register (PCC).
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
CHAPTER 27 INSTRUCTION SET
Clock
Operands Byte
Note 1
3 6
3 –
2 4
3 –
2 6
3 6
3 –
2 4
3 –
2 6
3 6
3 –
2 4
3 –
2 6
2 4
3 –
2 4
2 –
2 6
2 4
3 –
2 4
2 –
2 6
1 2
1 2
1 2
Operation
Note 2
7 CY CY (saddr.bit)
7 CY CY sfr.bit
– CY CY A.bit
7 CY CY PSW.bit
7 + n CY CY (HL).bit
7 CY CY (saddr.bit)
7 CY CY sfr.bit
– CY CY A.bit
7 CY CY PSW.bit
7 + n CY CY (HL).bit
7 CY CY (saddr.bit)
7 CY CY sfr.bit
– CY CY A.bit
7 CY CY PSW.bit
7 + n CY CY (HL).bit
6 (saddr.bit) 1
8 sfr.bit 1
– A.bit 1
6 PSW.bit 1
(HL).bit 1
8 + n + m
6 (saddr.bit) 0
8 sfr.bit 0
– A.bit 0
6 PSW.bit 0
(HL).bit 0
8 + n + m
– CY 1
– CY 0
– CY CY
) selected by the processor clock
CPU
Flag
Z AC CY
1
0
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