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Figure No.
23-3.
HALT Mode Release by RESET Input ...........................................................................................
23-4.
STOP Mode Release by Interrupt Request Generation ................................................................
23-5.
Release by STOP Mode RESET Input ..........................................................................................
24-1.
Block Diagram of Reset Function ..................................................................................................
24-2.
Timing of Reset Input by RESET Input ..........................................................................................
24-3.
Timing of Reset due to Watchdog Timer Overflow ........................................................................
24-4.
Timing of Reset Input in STOP Mode by RESET Input .................................................................
25-1.
Block Diagram of ROM Correction ................................................................................................
25-2.
Correction Address Registers 0 and 1 Format ..............................................................................
25-3.
Correction Control Register Format ..............................................................................................
25-4.
Storing Example to EEPROM (when one place is corrected) .......................................................
25-5.
Connecting Example with EEPROM (using 2-wire serial I/O mode) .............................................
25-6.
Initialization Routine ......................................................................................................................
25-7.
ROM Correction Operation ............................................................................................................
25-8.
ROM Correction Example .............................................................................................................
25-9.
Program Transition Diagram (when one place is corrected) .........................................................
25-10.
Program Transition Diagram (when two places are corrected) .....................................................
26-1.
Memory Size Switching Register Format ( PD78P054) ...............................................................
26-2.
Memory Size Switching Register Format ( PD78P058) ...............................................................
26-3.
Internal Expansion RAM Size Switching Register Format ............................................................
26-4.
Page Program Mode Flowchart .....................................................................................................
26-5.
Page Program Mode Timing ..........................................................................................................
26-6.
Byte Program Mode Flowchart ......................................................................................................
26-7.
Byte Program Mode Timing ...........................................................................................................
26-8.
PROM Read Timing ......................................................................................................................
B-1.
Development Tool Configuration ...................................................................................................
B-2.
EV-9200GC-80 Drawing (For Reference Only) .............................................................................
B-3.
EV-9200GC-80 Footprint (For Reference Only) ............................................................................
B-4.
TGK-080SDW Drawing (For Reference) (unit: mm) ......................................................................
32
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