Processor Clock Control Register Format - NEC PD75402A User Manual

Address 3 2 1
FB3H PCC3 PCC2 PCC1 PCC0
Note When using a calue of f
= 11) is set as CPU clock frequency, 1 machine cycle is less than 0.95 s and the standard minimum value
0.95 s is not kept.
Therefore, is this case, PCC1, PCC0 = 11 cannot be set, so it should be used with PCC1, PCC0 = 00 or 10.
As a result, the combination of "f
cycle = 0.95 s) as CPU clock.
56
CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS
Fig. 5-11 Processor Clock Control Register Format
0 Symbol
PCC
CPU clock selection bits when f
0 0
0 1
1 0
1 1
When 4.19 MHz < f
0 0
0 1
1 0
1 1
f : Main system clock oscillation circuit output frequency
XX
CPU operating mode control bit
0 0
0 1
1 0
1 1
such that 4.19 MHz < f
XX XX
= 4.19 MHz, PCC1, PCC0 = 11" is maximum speed selection (1 machin
XX
4.19 MHz
XX
( ) : When f
XX
CPU Clock Frequency
Output = f /64 (65.5 kHz)
XX
Setting prohibited
= f /8 (524 kHz)
XX
= f /4 (1.05 MHz)
XX
5.0 MHz
XX
( ) : When f
XX
CPU Clock Frequency
Output = f /64 (76.7 kHz)
XX
Setting prohibited
= f /8 (614 kHz)
XX
Setting prohibited
Normal operating mode
HALT mode
STOP mode
Setting prohibited
5.0 MHz, if maximum speed mode :
= 4.19 MHz
1 Machine Cycle
15.3 s
–
19.1 s
0.95 s
= 4.19 MHz
1 Machine Cycle
13 s
–
1.63 s
–
f /4 (PCC1, PCC0
XX