Logic Circuit Of Scl Signal - NEC PD78052 User Manual

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries)
Figure 17-29. Logic Circuit of SCL Signal
CLC (manipulated by bit manipulation instruction)
SCL Wait request signal
Serial clock (low while transfer is stopped)
Remarks 1. This figure indicates the relation of the signals and does not indicate the internal circuit.
2. CLC: Bit 3 of interrupt timing specify register (SINT)
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