Data Transmission From Master To Slave (Both Master And Slave Selected 9-Clock Wait) - NEC PD78052 User Manual

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries)
Figure 17-22. Data Transmission from Master to Slave
(Both Master and Slave Selected 9-Clock Wait) (1 of 3)
Master device operation
Write SIO0
COI
ACKD
CMDD
L
RELD
CLD
P27
H
L
WUP
L
BSYE
L
ACKE
CMDT
L
RELT
CLC
L
WREL
L
SIC
INTCSI0
Transfer line
SCL
SDA0
Slave device operation
Write SIO0
COI
ACKD
CMDD
L
RELD
CLD
P27
WUP
BSYE H
H
ACKE
L
CMDT
L
RELT
L
CLC
L
WREL
H
SIC
INTCSI0
CSIE0 H
L
P25
L
PM25
L
PM27
(a) Start Condition to Address
SIO0 Address
1 2 3 4 5 6 7 8 9
A6 A5 A4 A3 A2 A1 A0 W ACK
SIO0 Data
1 2 3 4 5
D7 D6 D5 D4 D3
SIO0 FFH
379