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Table 9-9. Interval Times when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2)
are Used as 16-Bit Timer/Event Counter
TCL13 TCL12 TCL11 TCL10
0
0
0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Other than above
Remarks 1. f
X
2. MCS
3. TCL10 to TCL13 : Bits 0 to 3 of timer clock select register (TCL1)
4. Values in parentheses when operated at f
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2
Minimum Interval Time
MCS = 1
MCS = 0
TI1 input cycle
TI1 input cycle
2
2
1/f
2
1/f
X
X
(400 ns)
(800 ns)
2
3
2
1/f
2
1/f
X
X
(800 ns)
(1.6 s)
3
4
2
1/f
2
1/f
X
X
(1.6 s)
(3.2 s)
4
5
2
1/f
2
1/f
X
X
(3.2 s)
(6.4 s)
5
6
2
1/f
2
1/f
X
X
(6.4 s)
(12.8 s)
6
7
2
1/f
2
1/f
X
X
(12.8 s)
(25.6 s)
7
8
2
1/f
2
1/f
X
X
(25.6 s)
(51.2 s)
8
9
2
1/f
2
1/f
X
X
(51.2 s)
(102.4 s)
9
10
2
1/f
2
1/f
X
X
(102.4 s)
(204.8 s)
11
12
2
1/f
2
1/f
X
X
(409.6 s)
(819.2 s)
Setting prohibited
: Main system clock oscillation frequency
: Oscillation mode selection register (OSMS) bit 0
Maximum Interval Time
MCS = 1
MCS = 0
8
2
TI1 input cycle
8
2
TI1 input cycle
17
18
2
1/f
2
1/f
X
X
(26.2 ms)
(52.4 ms)
18
19
2
1/f
2
1/f
X
X
(52.4 ms)
(104.9 ms)
19
20
2
1/f
2
1/f
X
X
(104.9 ms)
(209.7 ms)
20
21
2
1/f
2
1/f
X
X
(209.7 ms)
(419.4 ms)
21
22
2
1/f
2
1/f
X
X
(419.4 ms)
(838.9 ms)
22
23
2
1/f
2
1/f
X
X
(838.9 ms)
(1.7 s)
23
24
2
1/f
2
1/f
X
X
(1.7 s)
(3.4 s)
24
25
2
1/f
2
1/f
X
X
(3.4 s)
(6.7 s)
25
26
2
1/f
2
1/f
X
X
(6.7 s)
(13.4 s)
27
28
2
1/f
2
1/f
X
X
(26.8 s)
(53.7 s)
= 5.0 MHz.
X
Resolution
MCS = 1
MCS = 0
TI1 input edge cycle
TI1 input edge cycle
2
2
1/f
2
1/f
X
X
(400 ns)
(800 ns)
2
3
2
1/f
2
1/f
X
X
(800 ns)
(1.6 s)
3
4
2
1/f
2
1/f
X
X
(1.6 s)
(3.2 s)
4
5
2
1/f
2
1/f
X
X
(3.2 s)
(6.4 s)
5
6
2
1/f
2
1/f
X
X
(6.4 s)
(12.8 s)
6
7
2
1/f
2
1/f
X
X
(12.8 s)
(25.6 s)
7
8
2
1/f
2
1/f
X
X
(25.6 s)
(51.2 s)
8
9
2
1/f
2
1/f
X
X
(51.2 s)
(102.4 s)
9
10
2
1/f
2
1/f
X
X
(102.4 s)
(204.8 s)
11
12
2
1/f
2
1/f
X
X
(409.6 s)
(819.2 s)
235
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